Reprogrammable Logic: From Standard Logic Replacement To Unique Solutions
Programmable logic is the ubiquitous and versatile building block that virtually all digital systems rely on. Nowadays, it comes in several different types that can be programmed only once or reprogrammed time and time again. Programmable logic in the form of and/or plane-programmable logic arrays was developed at the beginning of the '70s. By 1972-73, it evolved into fuse-link, one-time field-programmable logic arrays (FPLAs) that permitted instant customization of the logic configuration.
Advances in architecture then led the former Monolithic Memories Inc. (MMI) to create programmable array logic (PAL). This simplified version of the PLA in a 20- or 24-pin package allowed designers to replace from about 5 to 20 gates of off-the-shelf logic. Along with these PALs, MMI also created a simple programming language (called PALASM) that made it easy to convert logic equations into bit-configuration patterns. Although MMI no longer exists, it laid the groundwork for the reprogrammable logic in widespread use today.
In the late '70s and early '80s, the incorporation of ultraviolet (UV) erasable and electrically erasable memory cells let designers wipe the logic configuration clean, then reprogram the programmable logic. UV EPROM-based devices, like those pioneered by Altera Corp. (www.altera.com), were reprogrammable, but they had to be removed from the board and then exposed to intense UV light before reprogramming. The use of EEPROM technology spearheaded by Lattice Semiconductor (www.latticesemi.com) eliminated the need to remove the device from the board while reprogramming.
In 1985 Xilinx (www.xilinx.com) switched to static RAM storage elements to hold configuration information, allowing logic to be changed just by updating the contents of the RAM cells. The Xilinx XC2010, with its complexity of about 2000 gates, gave birth to the field-programmable gate array (FPGA).
Logic densities during the '90s increased from the 2-kgate devices introduced in 1985 to today's chips that pack over 1 million gates, tens of kilobits of static RAM, and dedicated functions such as PCI cores, 16- or 32-bit embedded processors, or high-speed serial interfaces. Thanks to the SRAM configuration memory, the logic can be reconfigured to enhance performance, add new features, or work around flaws in the logic or silicon. Over the next year or two, watch for SRAM-based chips with up to about 3 million gates and 400 kbits of SRAM.
Gate delays in the logic arrays have become short enough to allow circuits to operate at clock speeds of several hundred megahertz, with some serial I/O ports able to handle data transfers at speeds of up to 3.125 Gbits/s. And, even faster FPGAs can be expected as densities increase thanks to the use of ever-smaller transistors and copper metallization.
However, SRAM-based FPGAs aren't the only reconfigurable solutions available to designers. Flash-based nonvolatile storage has been incorporated in an FPGA family now offered by Actel (www.actel.com). A company called Gatefield, acquired by Actel in 2000, developed the flash FPGA in the latter half of the '90s. Although not available with gate counts as high as those in SRAM FPGAs, the complexities of the flash-based FPGAs will hit the million-gate mark this year. Actel and rival QuickLogic (www.quicklogic.com) additionally offer families of one-time programmable FPGAs based on antifuse configuration elements.
One of the hottest trends that will be gaining momentum is the incorporation of reprogrammable blocks of logic onto standard-cell or full-custom ASICs. This allows designers to complete the bulk of their design, while permitting some post-fabrication logic customization. Companies like LSI Logic (www.lsilogic.com) and Atmel (www.atmel.com) have pioneered the use of such blocks. Adaptive Silicon (www.adaptivesilicon.com) has developed an FPGA "core" that ASIC designers can license and drop into a chip design. This helps to reduce the overall cycle time from concept to final product.
Increased availability of dedicated and configurable analog functions to provide a "real world" connection to digital system logic will greatly reduce system complexity and component count.
More dedicated on-chip functions will help reduce overall design time. More CPU choices will be available, as will functions like phase-locked loops, DRAM controllers, and high-speed serial interfaces.
In addition to the reprogrammable aspects, designers will find ways to reuse logic, reducing the amount of silicon needed to provide a system solution. Thus, on a cycle-by-cycle basis, the FPGA can be reconfigured to perform different functions.
The use of deep-submicron processes will permit very high-speed operation, perhaps 400 to 600 MHz for logic functions and up to 5 GHz for high-speed serial I/O interfaces.
Greatly improved functional capture, synthesis, and timing analysis tools will considerably reduce the design cycle time by minimizing the number of spins necessary to complete a design.
Increased use of multilevel copper metallization to reduce interconnect delays and allow seven or more layers of interconnect will improve the gate utilization on FPGAs and reduce propagation delays, increasing overall performance.
Blocks of FPGA gates will become megacells for use in ASICs, letting designers complete chips faster. Designers can then perform final logic configuration after processing by loading the desired logic bit pattern into the FPGA memory.
Greater availability of well-defined blocks of "soft" intellectual property. Design reuse will become more important as the complexity of a function continues to increase.
Much denser FPGAs will be released this year. Gate counts will hit 3 million by 2003 and close to 5 million by 2005. Such high gate counts will allow FPGAs to offer true system-on-a-chip (SoC) solutions.
The use of lower operating voltages will ensure that active power doesn't overwhelm designs as densities move toward the multimillion-gate realm. Overall power consumption will be an important issue because FPGA suppliers can't predict the functions that designers will instantiate in logic.