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Electronic Design

Digital PLL Cuts The Jitter In Sonet/SDH Networks

The ballooning amount of Sonet/SDH optical network applications made Silicon Laboratories quick to act. Its Si5318 clock multiplier, targeted at OC-48/STM-16 speed-level systems (2.488 Gbits/s), should also find use in systems that employ forward error correction and 10 Gigabit Ethernet networks.

The Si5318 suits OC-48 line cards that need a clean 155.52-MHz clock to drive the transceiver between the small form-factor pluggable (SFP) optical module and the framer/mapper circuits. It can take a clock input at 19.44, 38.88, 77.76, or 155.52 MHz and produce a jitter-minimized output clock at 19.44 or 155.52 MHz.

The internal phase-locked loop's wide tuning range (>11%) lets the chip accept a broad range of inputs near those clock inputs mentioned. The Si5318 reduces output jitter to as low as 0.7 ps rms. This is far lower than the Sonet/SDH requirements, giving engineers lots of design headroom in the overall jitter budget.

The secret to this superior jitter performance is Silicon Labs' patented digital signal processing PLL (DSPLL) with its DSP loop filter. Frequency dividers at the input and in the feedback loop are selectable to provide the desired output multiplication with the applied input. The loop filter bandwidth is programmable in five steps (800, 1600, 3200, and 6400 Hz and 12.8 kHz) to fine-tune the PLL for minimum jitter.

Other beneficial features include its digital hold of output frequency during a loss of input clock, a loss of input signal (LOS) alarm, and a hitless recovery from a digital hold when the input returns. Only a single resistor and bypass capacitor are required. The device runs from 3.3 V dc with a low power dissipation of 445 mW and comes in a 9- by 9-mm CBGA package.

The Si5318 costs $32 in 1000-unit quantities. Samples are available now. Full production is scheduled for July 2005. An evaluation board is available for $350.

See associated figure

Silicon Laboratories Inc.

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