With a large static RAM and a coprocessor on-board, DSP56307 digital signal processor is poised to give system throughput a major boost over what is achievable with existing DSPs. The chip design not only reduces wait states by allowing applications to run in the on-chip memory, it also uses its coprocessor to run applications in parallel, resulting in an impressive overall performance of 170 MIPS. In addition, the chip comes housed in a small, 15-mm square, 196-pin PBGA package that can accommodate dense, side-by-side packing for multiple-channel applications. Besides its independent filtering coprocessor and 64K x 24 bits of SRAM, this newest member of the 24-bit DSP56300 core family of programmable DSPs also has six channels of DMA, a triple timer, serial communications, and other I/O. And it reduces power consumption by employing split power planes, separating the I/O and peripheral sections, which operate at 3.0V to 3.6V, from the processor core running at 2.5V.
Company: MOTOROLA SEMICONDUCTOR PRODUCTS SECTOR (SPS)
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