Electronic Design

Dual-Port SRAM Accelerates Smart-Phone Development

Today's cell phones seem to do it all. Yet to meet these multimedia needs, handset manufacturers have to balance faster processors, more memory, and support circuitry against power demands. Specifically designed for cell phones, Integrated Device Technology's 70Pxx family of dual-port SRAMs tackles the challenge with greater simplicity and low power consumption.

Evolving 2.5G and 3G cell phones are a good example of the challenge designers face as they seek to reduce board space and power consumption while delivering high-performance handhelds loaded with multimedia gadgets. A typical smart phone incorporates various multimedia functions as well as location services and faster data transfer (see the figure). The baseband processor, usually DSP, handles the voice processing and related duties. The applications processor, typically a RISC processor like ARM or MIPS, manages the general housekeeping, MPEG video compression/decompression, and other functions like E911 location.

The communications link between these two processors, which share data, is a common bottleneck. UART and USB connections between the two processors are inadequate for today's smart phones. While each processor typically has its own memory, optimal performance is achieved only with some shared memory and data buffering.

This is where the 70Pxx chips come in. They increase communications bandwidth between processors, reduce design complexity, lower overall power consumption, and improve time-to-market.

The IDT 70Pxx family includes eight dual-port SRAMs with an access time of 55 ns, providing a 290-Mbit/s transfer rate per port. The 4k and 8k memories are 16 or 18 bits wide. Any location may be simultaneously read from or written to via either port.

The family starts with a 1.8-V core and I/O. Several versions have 3.3-, 3.0-, and 2.5-V I/O capability to reduce the need for special interfacing on the ports to either processor. Each model has separate input read and output write registers. Typical power consumption is only 27 mW with a 3.6-µA standby power drain.

The chips' 100-ball BGA package is 6 by 6 by 1 mm. An optional TQFP package is available as well. Prices run from $2.50 to $3.50 each in million-unit quantities.

Integrated Device Technology

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