“Can the PCB handle it?”
It’s a question I’ve batted back and forth with my colleagues many times over the years. And it usually comes in the wake of an overly confident salesperson who blindly and hastily committed to having a new higher-current power supply in a few weeks, with the details spelled out on a bar napkin from the golf club where the product was hatched. By the time the pain rolls downhill to the engineering department faced with building the widget, the conversation quickly turns into: “We have to get twice the current out of the same box as before. Can the PCB handle it?”
Printed-circuit-board (PCB) design textbooks and IPC standards do a good job of discussing a PCB trace’s dc current-carrying capability up to about 30 A. However, little if any reference material exists beyond this threshold, either in current or frequency. We know to avoid critical current densities that cause the traces to fuse open or delaminate from the PCB. But how far away do we need to be from these values and where, if at all, are these values listed?
The easiest way to begin this discussion is with a couple of common-sense boundaries on allowable current density in plain copper-wire conductors. The first of these comes from the transformer design world. In this world, designing a transformer for minimal temperature rise with virtually no cooling will use current densities of 1000 circular mils per ampere (CM/A). This is a lot of cross section for very little current. For instance, a 10-AWG conductor would be used to conduct no more than (10,400 CM)/(1000 CM/A) or roughly 10 A. We know that this is exceedingly conservative.
Another boundary, called “fusing,” can also evaluate the sensible current-carrying capability of a PCB trace. At some lower current density, the conductor will have enough localized heating to melt and fuse open. We certainly don’t want this to happen on our PCB!
The 14th edition of the EE Handbook\\[1\\]contains a chart on the fusing characteristics of copper on P 4-81.1 All of the tests that were performed used a one-inch-long conductor in free air. Clearly, these are very low current densities (CM/A) that shouldn’t be used on a PCB. This is where copper in the test specimen melts and fuses into the open state. The table need not be reproduced in this discussion, though is it a valid reference for the inquisitive engineer.
A PCB trace behaves a little differently. It’s flat with one side exposed to the air and the other laminated to the PCB material. However, as a common-sense boundary, the stated fusing current density for a 20-AWG wire (1020 CM cross section) at 10 seconds is about 45 A. At 0.1 seconds, it’s 450 A.
This is consistent with what we know of the I2t relationships of fusing. When there’s 45 A going through a 20-AWG wire, it corresponds to a current density of 22.2 CM/A. This is the current density that must be avoided. It may not fuse the trace open on a flat PCB with good exposure to air, but the trace will most assuredly overheat to discolor, peel, and degrade the surrounding laminate and traces on the PCB, and perhaps the components in the area.
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We can temper these boundaries by applying a little common sense. As a rule of thumb for safe current densities in copper wire, look at National Electronic Code (NEC) and National Fire Protection Agency (NFPA) guidelines for the residential wiring. NEC code for thermoplastic high-heat-resistant nylon-coated (THHN) wire in an applicable conduit pipe tells us that 12-AWG wire can handle 20 A of current safely in most any circumstance. (Of course, this is at 60 Hz, again with minimal skin effect loss in the wire.) This comes out to 327 CM/A, which is known to be a safe current density for copper. It’s been accepted for hundreds of years.
Transitioning from the well-known boundaries of wire conductors to lesser-known boundaries of planar conductors on a PCB, we need to consider PCB traces of different weights of copper, bottlenecks in the artwork, or any other planar attributes of the conductors. Here we’ll look at a well-accepted standard for PCB design—MIL-STD-275E. It can be found in numerous locations. (I dug it up at www.everyspec.com at www.dscc.dla.mil/Downloads/MilSpec/Docs/MIL-STD-275/std275.pdf.) This source offers a table that shows how much current can safely pass through a given trace in its Figure 4A (outer layer) and Figure 4B (inner layer).
This standard, drafted in 1984, doesn’t tell us anything about bottlenecks or current distributions. The tests ran on long, thin traces that carried fairly uniform currents. For a 20-A current and an aggressive temperature rise of 20°C, the specification recommends a trace with 700 square mils or 891 circular mils cross section. In 2-oz/sq ft copper, the nomograph calls out a trace that is 0.275 inches wide, while in 1-oz/sq ft copper, the trace is 0.550 inches wide. In terms of current density, this is about 45 CM/A.
The trouble with these standards is that they don’t include high enough currents for many of today’s applications. Multiphase synchronous buck converters can put out 20 A to 30 A per phase, summed to 150 A or so in some applications. Server power supplies are up in the hundreds of ampere outputs. The tables in the standards stop at 30 A in most cases, and they don’t talk about crowding or skin effect.
We know that the output traces of a switching power supply not only carry the dc current, but also the ripple current in some cases. Also, ripple currents have high frequency content and will flow along the surface of a thick conductor in accordance with the skin effect (Dpen = 7.6/√(f)), where f is the frequency in hertz and the result is the depth of penetration in copper in centimeters. To make this practical, at 300 kHz, Dpen is 0.014 cm, or 0.0055 inches, or 5.5 mils. Most switching converters still switch at low enough frequencies to utilize the majority of the trace thickness.
Crowding is another real phenomenon. Take, for example, a 3/8-inch output connector pin that solders into the PCB and is conducting around 100 A. A very wide a rectangular trace could be run to the pin, only to have the ends of the trace not be used at all. Current takes the path of least resistance. It will not flow along the edge of the trace and then turn and follow down and around to the large pin centered in the trace. It would be much more practical to make the large pin be the end point of a bottleneck and funnel the currents into the pin with tapered traces. This creates a uniform current distribution of the trace, and with a little guidance, the trace will be completely safe.
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I don’t have any deep mathematical rules for this procedure, as I’ve never needed them. In an environment with a lot of airflow, it’s possible to run current densities around 100 CM/A and size trace widths to this density. In areas of extreme bottlenecks, I never liked to dip below 30 CM/A. These are very short runs with ample copper or soldered components on both sides of the bottleneck to keep the low current density area cool.
In designs with little or no airflow, the old failsafe current density of 330 CM/A seems to work best, with bottlenecks having a current density no less than 100 CM/A. In long runs, which are nearly impossible at high currents without the help of busbars or board stiffeners, I’ve always gone with 500 or 1000 CM/A and then sized traces accordingly. The artwork will drive exceptions and curiosities, but we know the boundaries at least. Also, for buried layers, it’s preferable to use 30% more cross section because both sides of the trace have restricted cooling due to being surrounded by FR4 laminate.
For the more cost-effective materials like CEM 10 or Phenolic, I add 30% more cross section to any given trace since there’s reduced trace adhesion to the substrate. With thicker and thicker copper material, some diminishing return is evident on the trace width at higher currents. In other words, when going from 0.5-oz/sq ft copper to 4-oz/sq ft copper, a little more than one-eighth of the trace width may be needed to allow a little extra contact with the air. I haven’t seen this as a significant requirement.
This is probably the best point to introduce my wire table (see the table). I’ve been using this table to size wire and PCB traces for the last 15 years in applications varying from buried three-phase line sets, to a 480-V distribution transformer, to six-layer PCBs. The table translates wire size to cross section and, ultimately, trace width on a PCB. Also, there are added columns for equivalent trace width in 0.5-oz to 6-oz/sq ft copper and the current through the trace that would yield current densities of 30, 100, 300, 500, and 1000 CM/A.
It’s an easy tool to use. Say, for example, upon doing a layout review, you find a half-inch-wide trace in 2-oz/sq ft copper that’s carrying 200 A in a fan-cooled environment with lots of air flow. You simply find the 2-oz/sq ft column, drop down to the closest trace width (0.454 inches or 454 mils—the equivalent cross section of an 18-AWG wire), and move horizontally to the current-density columns. We see that the 30 CM/A current density column calls for a current of 54 A. The current is roughly four times larger than that, which is a problem. This trace needs to be at least four times wider if it’s a short bottleneck and 12 times wider if it’s a substantial run.
As another example, let’s say that you’re designing a multiphase buck converter at 300-kHz per phase and five phases total. The converter delivers 20 A per phase and has excellent airflow. The copper thickness on the PCB is 2 oz/sq foot or 2.8 mils. Simply find the 100-CM/A column and drop down to the value closest to 20 A (20.5 A in this case). Then look horizontally—this corresponds to the equivalent cross section of a 17-AWG wire and a trace that’s 575 mils wide in 2-oz/sq foot copper. If a trace is copied onto multiple layers, the inside needs to be derated as discussed above, but the layers can use proportionally thinner traces. The output would require a 2900-mil-wide trace if on one single layer.
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In this example, it’s easy enough to refute these guidelines on trace width. Most motherboard designs and VRM modules use much smaller traces due to the very short traces used. However, you will find that they never drop below the 30-CM/A guideline and they rely on the component masses, solder, heatsinks, etc., to pull heat out of the whole system, including the traces. It’s also noteworthy to mention that the output frequency will be 1.5 MHz into the capacitor bank. The depth of penetration in this trace will be roughly 2.4 mils, so the ripple currents will flow through most of the trace.
The table offers other features like resistance of the conductor (ohms per foot), via cross sections, temperature classifications, and equivalent square mil and square millimeter cross sections. This isn’t rare or obscure information, but rather a collective means to show well known guidelines and a handy tool.
I’ve heard that high-end PCB design and circuit-simulation tools actually have built-in programs to size PCB traces. Since I haven’t used these programs, I can’t comment on their effectiveness or correlate them to common-sense current-density values.
The PCB design world continues to push toward higher and higher power densities. Therefore, PCB traces carry more and more current per unit cross section. As a result, designers must have a reasonable understanding of a PCB’s current-carrying capabilities and, perhaps, follow a couple rules of thumb. Also, I have triangulated the fundamental cross-section values with numerous sources from the U.S. Navy to the NEC code book. I maintain the utmost confidence in the validity of the baseline data.
Reference
- Fink, Donald G., and Beaty, H. Wayne, Standard Handbook For Electrical Engineers, 14th Edition; McGraw-Hill Professional, Oct. 1, 1999, ISBN 0-07-022005-0.