An on-chip Level 2 cache significantly boosts the performance of the RM7000, a high-performance MIPS RISC embedded microprocessor. The processor is intended for applications such as network routers/switches, printers, game systems, low-end workstations, 3D accelerators, and industrial control and vision systems.Performance specifications include estimated benchmarks at a 300-MHz clock rate of 12 to 14 for SPECint95 and 14 to 16 for SPECfp95. The chip implements the MIPS IV instruction set architecture and features system address/data bus maximum performance at 125 MHz for a 1000-Mbyte/s peak data transfer rate. Other key features include: superscalar instruction issue with dual-integer issue, non-blocking caches; a 16-kbyte instruction cache and 16-kbyte Level 1 data cache, both of which are four-way set associative; and an integrated 256-kbyte, non-blocking Level 2 cache, which also is four-way set associative.The firm's benchmarks for networking applications are said to show that the RM7000 system performance is 3.7 to 6.7 times faster than the RM5271 at 200 MHz. The boost comes from three main areas of improvement: raw compute power, memory hierarchy and interrupt handling. Raw compute power was increased by nearly 100% thanks to the RM7000's 300-MHz CPU and dual-integer issue capability. Memory hierarchy improvement is the result of the on-chip L2 cache and the use of a data pre-fetch instruction as well as the non-blocking nature of both caches. And an order-of-magnitude improvement in interrupt handling is achieved by virtue of additional hardware support for priority and vectoring, with a worst-case latency of 166 ns when the handler is locked in cache. The RM7000 embedded MIPS RISC processor is available now with volume production slated for the third quarter.