Electronic Design

Exercise And Analyze Your ASI Chip-Set Designs

The Advanced Switching Interconnect (ASI) switched-fabric interconnect standard links computer components such as CPU and I/O nodes in multiple topologies. Now, engineers working on ASI chip sets have the support needed to comprehensively verify their designs.

The E2980A series ASI protocol test solution provides protocol analysis and exercising capability for ASI. Developed by Agilent Technologies, it offers complete test coverage of single or multiple ASI interfaces from first silicon to board turn-on to overall system verification.

The protocol analyzer acts as an active ASI device that can generate and respond to all types of ASI packets and sequences of packets. It allows emulation of large ASI fabrics, enabling the testing of BIOS software, drivers, and switches. Users can insert errors and then check their design's behavior.

Also, the protocol analyzer permits non-intrusive traffic monitoring between two ASI end nodes. It brings dynamic triggering, search and filter capabilities, and sophisticated usability and traffic representations. Such features result in fast debug, detailed root-cause analysis, and device performance analysis. Triggers are set up graphically (see the figure).

The E2980A can be ordered now, with shipments beginning in May. The protocol exercisers go for $62,000, and the protocol analyzers start at $58,000. E2960A for PCI Express owners can upgrade to an E2980A for ASI for $29,000.

Agilent Technologies Inc.

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