When the convenience of pushbutton control is desired in a design, the first option considered by the designer might be a keypad scanner-encoder-latch scheme that uses commercially available devices. This choice proves sound and economically feasible when more than five buttons are involved, but isn’t optimum if four or less are required. The solution for the latter situation is to employ one of the debouncer/latch/decoder (DLD) circuits described here. Using only a few ICs plus some discrete components, this family of circuits guarantees foolproof operation and offers minimal power consumption due to their static nature.
The basic arrangement for a “1-of- 2” DLD is shown in Figure 1. It’s instantly recognized to be two NANDgate RS flip-flops connected one to the other, but its simplicity deceives because its operating characteristics aren’t so obvious. To proceed with a circuit analysis, an initial state for these flip-flops must be established.
Assuming that —OUT2 is low and all capacitors are charged to VDD, then U1A’s output also will be low. Depressing PB2 will do nothing to alter these conditions, because —IN2 being low only reinforces U1A’s low input to U1B. Next, PB1 is depressed while still pushing PB2. With —IN1 now low, the outputs of both U1A and U1B are high. Therefore, U1A/U1B no longer can influence U1C/U1D’s state and —OU —T2 still remains low. This demonstrates that the U1A/U1B flip-flop effectively discriminates against invalid input combinations. Releasing only PB1 does not change —OU —T2, but does force U1A’s output low again. Finally, releasing PB2 lets the entire circuit return to the initial conditions assumed.
Pressing PB1 alone will cause both flip-flops to change state with —OU —T1 now low. Depressing and then releasing PB2 can’t alter this new output condition. But, what happens after both buttons are depressed and PB1 is released first? With PB2 still depressed, the output will immediately change to —OU —T2 = low. This operating feature is known as keyboard rollover, another valuable asset of the circuit.
The latch and decoder qualities of this circuit are now apparent. Moreover, because it’s accepted practice to employ an RS flip-flop to buffer circuitry from inherent pushbutton bounce, U1A/U1B also serve as the circuit’s debouncer. All from only one IC!
The R1/C1 and R2/C2 networks function as noise and bounce filters for the pushbuttons. It’s true that when a pushbutton is first depressed, it’s fundamentally shorting out a capacitor. However, this isn’t entirely detrimental. Contacts of most mechanical switches and relays will oxidize or tarnish over time. This momentary surge of current provided by the capacitors helps keep them clean. Of course, if the capacitor is too large, the plating on the contacts could be vaporized, but not with 0.005 mF supplying the charge.
D1, R3, and C3 force the DLD to initialize properly during power up. These components pull the selected rail low for a short time (approximately 0.7R2C3), setting its associated output, —OU —T2, low. D1 is reversed-biased when the pushbutton is depressed, disconnecting any effects of this auxiliary circuit. If a three-input NAND gate was used for U1B, initialization could be applied to its third input pin using only R3 and C3. D1 is thereby eliminated and C3’s value could be much smaller.
The rest of the family includes the “1-of-3” DLD (Fig. 2) and the “1-of-4” DLD (Fig. 3). Each of the these circuits exhibit the same foolproof and reliable operating characteristics as the “1-of-2” DLD, only on a larger scale. To simplify their presentations, these schematics are devoid of pushbuttons and support circuitry.
Notice that only three ICs are needed for the “1-of-3.” The “1-of-4” is somewhat of a hybrid, because two different logic-gate types are incorporated in its design. The reason for this deviation is that this version could be built using eight 8-input NAND gates, but one input on each gate would be wasted. This preferable design allows no waste and yields a spare three-input AND gate for other uses. Nevertheless, the “1-of-4” requires seven ICs. A “1-of-5” also could be implemented with ten 8-input NAND gates, but this definitely encroaches into the scanner-encoder-latch domain.