Electronic Design
FPGA Combines Hard-Core Cortex-M3 And Analog Peripherals

FPGA Combines Hard-Core Cortex-M3 And Analog Peripherals

Actel is about to turn the microcontroller market on its end with its flash-based SmartFusion FPGA (Fig. 1), which incorporates an ARM Cortex-M3 microcontroller complete with peripherals such as serial ports and an eight-channel DMA. This combination alone would be impressive, yet SmartFusion also includes a configurable analog subsystem.

With up to 500,000 gates, the analog subsystem isn’t as customizable as the FPGA subsystem. But it is equally impressive and very powerful, incorporating its own digital processing engines to massage the digital side of the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

The flash-based aspect of SmartFusion is key in two areas. First, along with on-chip RAM, it enables a single-chip solution. Second, it means the chip is up and running quickly. RAM-based FPGAs must first load their configuration from a serial flash memory chip. The use of flash technology allows up to 512 kbytes of application code and data for the Cortex-M3 to reside on chip as well.

On-chip SRAM tops out at 64 kbytes. The processor subsystem includes an external memory controller so the use of large amounts of off-chip memory is possible in addition to its ability to handle removable storage. There are also up to 41 I/O ports. The FPGA has an additional 128 I/O ports.

The 32-bit processor subsystem runs at 100 MHz, while the FPGA and analog subsystems are clocked at 350 MHz. The 12-bit ADCs run at up to 600 ksamples/s. The DACs are sigma-delta DACs. On-chip voltage, current, and temperature monitors along with 32 analog inputs can be tied to up to ten 50-ns comparators and the ADCs. The processor communicates with the analog compute engine that controls the DACs and ADCs. This essentially implements a multicore analog compute environment.

The FPGA gives developers great flexibility, including the option to augment the Cortex-M3 with additional soft-core processors such as a Cortex-M1 if necessary (see “FPGAs Pushing MCUs As The Platform Of Choice”). The Cortex-M1 is code-compatible with the Cortex-M3, but it’s designed for FPGA implementations. The hard-core Cortex-M3 is a more efficient implementation, though the ability to construct a custom multicore platform will be very useful in many applications.


FPGAs have never been the easiest platform to work with from a software perspective, and dealing with lots of flexibility around a hard core could lead to programmer overload. That’s why Actel developed the MSS (Microcontroller SubSystem) Configurator. This software tool spans Actel’s Libero FPGA design suite and programmer integrated development environments (IDEs) such as those from Keil and IAR and Actel’s own Eclipse-based SoftConsole (see “A Total Eclipse?”) .

On the Libero side, MSS Configurator lays the groundwork for the Cortex-M3 and its peripherals. FPGA designers select configuration options as well as connections to the other subsystems. This allows MSS Configurator to generate the appropriate configuration as well as build and header files for software development.

Software developers can utilize the output of MSS Configurator and target platforms with preconfigured FPGA and analog support. They can also make more limited adjustments without needing to deal with FPGA designs and the complexity of RTL and FPGA design flows. Of course, some designers work on both sides of the fence. For them, MSS Configurator provides a mechanism that is consistent for both tool chains. This includes support for encryption IP.

The chip itself supports Actel’s FlashLock AES decryption when programming the FPGA. The software tool support includes a free GNU-based toolset as well as tool suites from IAR and Keil. The chip supports Arm’s CMSIS (Cortex Microcontroller Software Interface Standard) hardware abstraction layer (HAL). Micrium is providing middleware and operating system (OS) support, though the platform supports a range of operating systems.

Actel is initially delivering a low-cost $99 demo board (Fig. 2) and a $999 evaluation kit (Fig. 3). The kit provides access to all the I/O on the chip as well as more on-board RAM and flash memory. Both have an interface connector that works with daughter cards like the one for the Mixed-Signal Power Manager (MPM). The connector is designed for testing with a range of applications including motor control.

SmartFusion should have a major impact on how designers create applications solutions. The A2F200 will be the first SmartFusion chip available. Priced around $20, it has 200k gates, two ADCs, two DACs, 24 analog inputs, two analog outputs, 41 processor I/O ports, and 94 FPGA I/O ports. The FPGA has 4 kbytes of RAM, while the processor has 256 kbytes of flash and 64 kbytes of SRAM. The A2F200 will be bracketed by the A2F060 and the A2F500 with 60k gates and 500k gates respectively and a corresponding I/O complement.

SmartFusion looks to be the game changer that FPGAs have promised for software developers. This is especially true for designers who need a single-chip solution.


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