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FPGA Design Flow Tool Added To EDA Package

An FPGA design flow tool has been added to A|RT Designer 2.3, aC-language-based, system-level EDA software package that lets designers optimize hardware architectures in FPGAs using SystemC or ANSI-C algorithms. The tool’s several components tap the special architectures of Xilinx and Altera FPGAs, including automated memory optimization routines that maximize the utilization of limited on-board SRAM and the ability to create special datapath resources based on C-code, the execute multi-cycle DSP algorithms in a single clock cycle. Version 2.3 automatically searches the program for all instances of the relevant code segment and replaces it with the single-cycle datapath resource. This ability to parallelize the design is critical for FPGAs because they are much slower than ASICs or DSPs. The flow tool is available for HP-UX, Sun Solaris and Windows NT platforms and is priced starting at $45,000.


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