With an eye toward easing the system-level FPGA design process, version 8.0 of Actel’s Libero integrated design environment (IDE) enables users to design at a higher level of abstraction. Actel’s Smart- Design technology lets users visually create and then automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components.
The graphical block-based design entry supports prefabricated blocks from Actel’s extensive DirectCore and SmartGen IP libraries. It also supports custom blocks created in HDL or Synplify DSP and processor subsystems created with Actel’s Core- Console tool.
The SmartDesign capability allows source file components (such as SmartGen- and CoreConsole-configured IP and processor cores, HDL modules, Actel cell macros, and Libero-created blocks) to be visually grouped on a white-board “canvas” in a block-diagram view.
A “catalog” provides an extensive list of IP, macros, HDL templates, and bus interfaces that can be selected and dragged and dropped onto the canvas. Thus, SmartDesign facilitates real design reuse and paves the way for future block capture designs using system Verilog, DSP, mixed hardware/software blocks, and more.
The Actel Libero IDE 8.0 Platinum edition is available on Windows and Linux platforms for $2495. A free limited-feature Gold edition is avail- able for Windows. All editions are one-year renewable licenses. Version 8.0 of the Libero IDE supports all the company’s FPGAs, including the flash-based, low-power ProASIC3 and 5-µW Actel Igloo FPGAs, as well as the company’s Fusion programmable system chip (PSC), a mixed-signal power-management FPGA.