FPGA Family Taps New Architecture To Achieve Fast Internal Core Speeds

Built using the company’s new AX architecture that is said to integrate a number of new logic, routing, clock management, I/O and embedded features and functionality, the Axcelerator family of field-programmable gate arrays (FPGAs) reportedly eclipse by a considerable margin the speed and logic utilization of any existing FPGAs. Based on a 0.15-µm, seven-layer metal antifuse process, the new FPGAs range in density from 125,000 to two-million system gates and achieve internal core speeds of over 500 MHz with up to 100% resource utilization. The first members of the Axcelerator family to go commercial are the AX1000 and AX2000. With one million system gates, the AX1000 supports up to 199 Kb of embedded SRAM, 516 user I/Os, 6,048 dedicated flip-flops, eight global clocks, and eight PLLs. With two million system gates, the AX2000 supports up to 339 Kb of embedded SRAM, 684 user I/Os, 10,752 dedicated flip-flops, eight global clocks, and eight PLLs. The FPGA family is supported by the company’s Libero 2.2 integrated design environment and Designer Series tool suite, which includes place and route, timing analysis and memory generation functionality. A complete evaluation board is also available. The AX1000 and AX2000 are available as samples with production scheduled to begin in Q4. Pricing begins at $255 and $628 in volume, respectively. ACTEL CORP., Sunnyvale, CA. (888) 992-2835.