Electronic Design

FPGA Q&A: Altera

Electronic Design held a series of Q&A sessions with several major FPGA companies. Here, our discussion with Altera was a one-one-one with Greg Steinke, director of system applications engineering.

Question: What are the top five to 10 issues your applications engineers deal with on an ongoing basis? How are problems handled at the customer level, and how are they addressed by the company as a whole?


  1. Power consumption: Quartus II software’s PowerPlay power analysis and optimization technology, along with the Stratix III Programmable Power Technology, enables customers to dramatically lower power in their designs.
  2. Performance optimization: Concerns center around hitting FMAX, but also at a system-level (e.g., having sufficient throughput through a PCI Express interface). Quartus II software’s TimeQuest timing analyzer, which provides accurate prediction of timing, allows designers to customize the timing constraints to the system’s requirements.
  3. Debugging: Historically, an engineer would use a logic analyzer on the device’s pins. However, with the capacity of today’s FPGAs, many components are integrated into one device, and the logic analyzer can’t probe inside the design. The SignalTap II logic analyzer is a system-level debugging tool that captures and displays real-time signal behavior in a system-on-a-programmable-chip (SOPC), giving designers the ability to observe interactions between hardware and software in system designs.
  4. Interface complexity: The interfaces used by systems are more complex to achieve higher performance (e.g., a DDR2 SDRAM interface is more complex than an older SRAM interface). Altera offers a variety of IP cores that lets designers easily implement the needed interfaces.
  5. Signal integrity: Altera offers a variety of models, including HSPICE and IBIS, along with built-in on-chip termination, which helps to ensure that signals get from point A to point B correctly.
  6. System complexity: Designers face the task of building complex systems in the same amount of time as prior, less complex projects. Altera provides IP cores, system validation, and board-layout tools that ease design development on common portions of the system, and allows customers to focus on their differentiating factors.

Question: What flow do you suggest your customers follow when starting a new FPGA design?

Answer: It really depends on what you are trying to do.

For DSP designs, a designer can use the DSP Builder tool, which links with Matlab and Simulink. The designer can create the hardware representation of a DSP design in an algorithm-friendly development environment. The existing Matlab functions and Simulink blocks can be combined with Altera DSP Builder blocks and Altera IP MegaCore functions to link system-level design and implementation with DSP algorithm development. DSP Builder allows system, algorithm, and hardware designers to share a common development platform. (For more details, see the DSP Builder Web page at www.altera.com/products/software/products/dsp/dsp-builder.html.)

For systems with an embedded processor, or combining multiple IP blocks, a designer can use SOPC Builder to quickly create the overall system. Furthermore, an engineer is able to create custom SOPC Builder components to integrate into the system. (For details, refer to the SOPC Builder page at www.altera.com/products/software/products/sopc/sop-index.html.)

For general logic, customers can turn to Verilog, VHDL, or schematic entry, either directly with the Quartus II tool or with other synthesis tools.

Once the pinouts are set, the Quartus II software can generate pin files that are generated into schematic tools. Or, a board designer is able to create the FPGA pinouts in a tool and import them into the Quartus II software. Quartus II software directly supports Cadence’s Allegro software and Mentor Graphics’ DXDesigner and I/O Designer software. Furthermore, the Quartus II software can generate an ASCII file containing the pin assignments.

Altera and its partners provide reference designs for common applications that can serve as a starting point for a design. One example is an Automotive Graphics reference design that shows how to use an Altera FPGA in an automobile graphics system. This reference design demonstrates how to bring in the video and control a thin-film-transistor (TFT) display, including picture-in-picture. For more information, see the Reference Designs page at www.altera.com/end-markets/refdesigns/ref-index.jsp.

Altera and its partners provide development kits that allow customers to create proof-of-concept designs before committing to a board layout. These have a variety of connectors to enable integration into other systems for design verification. For more information, see the Altera Development Kits page at www.altera.com/products/devkits/kit-dev_platforms.jsp.

Question: What is normally suggested to your customers regarding the handling of I/O signal assignments? In what order do you suggest the various signal types be assigned? (That is, start with VREF, move to high-speed I/O, and so on.)

Answer: While flexible pin assignments are important in an FPGA, some degree of specialization helps to improve signal integrity and, therefore, system performance by reducing pin capacitance. For example, pins used on a high-speed transceiver (such as PCI Express) can’t be employed as general-purpose IOs. Altera doesn’t require that pins be assigned in a certain sequence, but the pin assignments need to match the pin capabilities. A customer can use Quartus II software to perform a pin check before starting a design, allowing for board and chip design to be done concurrently.

Question: What approach do you suggest to your customers when dealing with incompatible I/O standards, different voltage references, and other issues with respect to bank or region compatibility?

Answer: Altera’s goal is to make this as easy for customers as possible. To this end, we enable pins to support multiple I/O standards across multiple voltages (e.g., a pin that is powered by a 2.5-V supply can still accept 3.3-V inputs on most devices). Also, most pins are designed to enable hot socketing, where the FPGA can act as the interface on the board that’s being plugged into a live system. This feature is important even when hot socketing isn’t intended. A system with multiple voltage supplies may have them power up in various orders. Thus, Altera’s FPGAs are designed so that a system may power up the core voltage, various I/O bank voltages, and signals driving into the device in any order. By doing so, a designer can accommodate other chips that may need to be power-sequenced in a certain order, or simply have one less thing to worry about.

Question: How do you tell your customers to prepare for a migration path to another FPGA, a structured ASIC, or ASIC?


  1. Another FPGA: If switching from one FPGA to another in the same family, we offer pin migration. If switching from one family to another, a board spin is generally required, as the pinouts will be different. By using MegaFunctions (such as lpm_mult), a designer can ensure that he will be getting the most out of specialized blocks, such as the DSP blocks.
  2. Structured ASIC: Altera recommends use of the HardCopy II devices as a structured ASIC. Selecting the HardCopy option in Quartus II software eases the transition to a structured ASIC, for example, by ensuring that the pins used will map from the FPGA to the HardCopy II device. Another key point is that blocks such as memories, LVDS interface, or phase-locked loops (PLLs) are the same on the HardCopy II device as on the FPGA, enabling easy migration.
  3. ASIC: Porting logic from an FPGA to an ASIC (such as is done when prototyping) is relatively easy. However, it becomes a challenge when migrating from an FPGA to an ASIC, because blocks such as PLLs or memories may not function exactly the same. Because we don’t know exactly how ASIC blocks will function, giving advice here is outside of our expertise.

Question: What advice do you give to your customers when integrating their FPGA device to the pc board (PCB) with respect to SSO/SSN? Decoupling? Routability? Escape area and escape planning with respect to signal layers? Thermal Issues?

Answer: Altera offers a variety of literature (www.altera.com/literature/lit-index.html) and net seminars (www.altera.com/education/net_seminars/ns-index.html) that address these topics. Published escape routes can be copied and used by customers. PowerPlay power analysis and optimization technology helps users understand how much power capabilities are in use. We also offer extended temperature devices if a designer finds that the device will be exposed to high temperatures.

Question: Do you provide specific advice for dealing with differential signals? If yes, what is it?

Answer: We offer on-chip termination for LVDS and differentials. Also, keep signals closely coupled. For more information, see the High-Speed Board Layout Guidelines paper at www.altera.com/literature/hb/stx2/stx2_sii52012.pdf.

Question: How do you recommend global and local/regional clocking be handled?

Answer: We don’t get a lot of questions about this. Page 48 of the Stratix II Architecture document describes the variety of clocks in Stratix II FPGAs: www.altera.com/literature/hb/stx2/stx2_sii51002.pdf. Our tools do a good job of selecting the best clocks to use.

Question: What issues are you seeing with combining IP blocks? What advice can you give for engineers shopping for IP?

Answer: The vision of SOPC Builder, Altera’s automated system-development tool, is that it be used with all IP. Customers can use SOPC Builder to tie the IP blocks together and build a component. More information is discussed under the topic “What flow do you suggest your customers follow when starting a new FPGA design?”

Question: What sorts of timing issues are causing the biggest problems, and how do you suggest they be handled?


  1. In-chip: FMAX; TimeQuest timing analyzer and physical synthesis helps.
  2. Off-chip: Source synchronous used for many interfaces with LVDS; the TimeQuest timing analyzer can also be used for source-synchronous interfaces. See the TimeQuest Example:Basic Source Synchronous Output Web page at www.altera.com/support/examples/timequest/exm-tq-basic-source-sync.htm.

Question: Do you have any recommendations for FPGA engineers working with other members of their team, like the layout engineer, systems engineer, and so on? What team approach should be applied to complex and/or high-speed FPGA designs?


  1. Board engineer: Suite of analog models (HSPICE, IBIS) for board simulation
  2. Team-based design: Quartus II can generate a pin file to generate schematic layout

Question: How do you help your customers get from concept to manufacturing?


  1. Concept to first stage of design: Altera offers development kits that help to prove the idea. The company also offers OrCAD Capture schematics available for our development kits, which are used to speed board design.
  2. Going to production: Altera’s operational excellence includes its track record of reliably hitting schedules.
  3. After production: In-field reconfiguration

HardCopy-structured ASICs for high volumes

Question: Are you working with EDA companies to better define up-front constraints that ideally could be applied and live with the FPGA throughout the design process?

Answer: Yes, we work with a variety of EDA partners. Altera’s ACCESS program shares device, software, and IP information with these partners to ensure a smooth design flow. See the EDA Partners page at www.altera.com/products/software/partners/eda_partners/eda-index.html.

Question: What additions or modifications are you making to your tool suite to help engineers overcome the issues discussed above?

Answer: It’s hard to quantify, but quality of tools is a focus for Altera. The company is focused on providing easy-to-use tools that deliver a high quality of results. This includes putting lots of emphasis on eliminating internal errors and crashes, as well as reducing compile time and PC memory usage.

PowerPlay power analysis and optimization technology gives designers the ability to accurately analyze and optimize dynamic and static power consumption. The PowerPlay power-analysis tools also enable pushbutton optimization of static and dynamic power consumption, as well as speed and area requirements. See the Quartus II PowerPlay Power Analysis and Optimization Technology page at www.altera.com/products/software/products/quartus2/design/qts-power_analysis.html#optimization#optimization.

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