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FPGAs Deliver Programmable Solution For SPI 4.2 Systems

By combining aspects of ASIC and FPGA approaches on the same chip, Lattice Semiconductor's ORSPI4 offers a high-speed programmable solution. It packs two system packet interface (SPI) 4.2 cores, an embedded quad-data-rate static memory controller with dual 36-bit data ports and an 18-bit address bus, 16k programmable four-input lookup-table logic elements, and 147 kbits of dedicated, distributed SRAM.

Four serializer/deserializer (SERDES) channels handle data rates from 600 Mbits/s to 3.7 Gbits/s. They also include 8b/10b encoding and decoding logic. Implementation of the SPI cores, SERDES channels, and memory controller takes about 1 million ASIC gates.

Each SPI 4.2 port, which is a full SPI 4.2 interface, supports all of the standard signals. The ports handle packet transfers between a media-access-controller device and a network processor or switch fabric, delivering a 14.4-Gbit/s aggregate bandwidth per port. Each SPI 4.2 interface has 16 bidirectional low-voltage differential-signal pairs for each transmit and receive channel operating at a data rate of 900 MHz.

Each SPI on the receive side supports static and dynamic packet alignment as well as both DIP-4 and DIP-2 parity generation and checking. Embedded dual-port RAMs provide 8 kbytes of data buffering on each port. Scheduling of up to 256 ports is supported by internal 1k deep main and shadow calendar. One of the two SPIs can either serve as the SPI 4.2 interface or be used as a four-channel SERDES interface for driving long pc-board traces.

The chip's FPGA portion is based on the ORCA Series 4 FPGA architecture Lattice acquired from Agere. It contains over 16k lookup tables, high-performance analog phase-locked loops, and many configurable I/O pads. The ORSPI4 FPGA comes in an 1156-contact plastic ball grid array (BGA) with 352 I/O pins or a 1036-ball thermally enhanced BGA with 496 I/O pins.

In 10,000-unit lots, the 1036-contact version costs $250 each. The lower-cost plastic BGA version comes without the SERDES channels. Both are supported by Lattice's ispLEVER v. 3.1 design software, a dedicated design kit, and popular third-party synthesis, simulation, and verification tools.

Lattice Semiconductor Corp.

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