The electronic-design-automation (EDA) industry seeks to provide a crystal ball of sorts. Using EDA tools, designers and architects can predict many aspects of a chip's performance. When it comes to functional verification, however, the answers get murky. It can be hard to tell if a design meets its architectural and functional specifications. Such uncertainty can be harmful, as those specifications dictate the design's correct functioning.
Many EDA companies are working on ways to improve functional verification. Mentor Graphics Corp., for example, recently announced the availability of ADVance MSTM (ADMS) version 4.0 (see figure). This version delivers full language support for SystemVerilog, SystemC VHDL, Verilog, SPICE, VHDL-AMS, Verilog-AMS, and C. In doing so, it hopes to give users the ability to perform block-level validation and full-chip functional verification in a single simulation environment. That environment spans from the system-specification stage to the post-layout verification stage.
This single, common platform extends both digital and analog verification for mixed-signal designs. It facilitates digital-centric verification like testbenches (directed and pseudo-random testing). At the same time, it allows analog-centric verification, such as circuit simulation (DC, AC, Transient, Parametric, Monte Carlo, and Corner). ADMS version 4.0 also enables mixed-signal-centric verification like "checkerboard" analysis.
By integrating with Verisity SpecMan Elite, ADMS 4.0 vows to facilitate the complex verification strategies that are required for new mixed-signal designs. This integration enables the early verification of architectural or partitioning decisions, which can be reused as testbenches throughout the design process. As a result, fundamental design flaws can be discovered and corrected earlier and more easily.
For companies that utilize geographically dispersed design teams, ADMS offers each team the ability to perform block-level verification in its preferred language. When blocks are brought together for full-chip implementation, including intellectual property (IP) from other sources, ADMS 4.0 can be used for final, full-chip verification. By preserving design elements in their native language, it alleviates the risk of data compatibility and integrity problems. It also reveals the functional flaws that can occur when using multiple verification tools.
ADMS promises to integrate seamlessly with any design flow. Pricing for ADVance MS 4.0 starts at $110,000 in North America. It will be available this quarter for Linux, HP, and Sun platforms. For more information, please visit the company's web site at www.mentor.com.