Electronic Design
Get Ready For Low Power And More Multicore In 2010

Get Ready For Low Power And More Multicore In 2010

There has never been a more exciting time for digital technology than the year ahead. Microcontrollers are getting smaller and running off of scavenged power. A 3- by 3-mm chip is tiny, but smaller chips house 8-bit and 16-bit processors. And, 32-bit micros cost well under $1 and are challenging the 8-bit and 16-bit competition when it comes to power usage.

High-end systems have gone after multicore with a vengeance. GPUs already have hundreds of cores in a chip, but they are specialized. Still, GPUs have taken high-performance computing to a new level at a price that’s astounding. Hundred-core chips with conventional CPUs are on the horizon for 2010.
Likewise, high-speed interconnects like USB are now moving into their third generation. Trying to keep ahead of the rest of the hardware is a challenge. For now, it looks like the products will be here when designers need them, which is right now.

New chips rarely come out without a development kit or two. Simple breadboard kits are still the norm, though the amount and quality of the bundled software has risen significantly over the years while the price for kits has fallen dramatically. This has made evaluation easier. It also has made the tools readily available to a wider variety of developers.
The reasoning that a larger community leads to more projects and more purchases is in full swing. Yet simply having a decent development kit is no longer a way to get recognition. In 2010, designers will need to do more than box up a pretty board and DVD, especially with the likes of Texas Instruments (TI) shipping head-turning designs like the eZ430-Chronos (Fig. 1).
Joining a long line of eZ430 kits, the eZ430-Chronos is a complete wireless development kit for the MSP430 16-bit microcontroller. Priced at only $49, the watch houses a CC430 wireless microcontroller. The kit also comes with a USB-based programmer and a USB-based wireless access point that ties the watch wirelessly to a PC.
The wireless link can connect to other devices such as the wireless heart-rate monitors from BM Innovations. The watch has an integrated battery, temperature, pressure sensor, and 3D accelerometer. Its use in exercise is obvious, but other projects can take the device in other directions. 
Also, look for even more migration to Eclipse as a base development platform. TI’s Code Composer Essentials for the eZ430-Chronos is Eclipse-based. NXP’s Eclipse incarnation, LPCXpresso, has a simplified interface designed to appeal to microcontroller developers and be used with integrated development environments (IDEs) that are more tailored for micro development. It provides ease of use with the ability to take advantage of other Eclipse plug-ins.

Intel’s Larabee, a multicore x86 CPU with GPU aspirations, won’t be knocking around with the GPU giants just yet. But it’s only one of dozens of projects the company has on tap in its worldwide labs. For example, Intel’s “single-chip cloud computer” (SCC) packs 48 IA-32 cores into a single chip (Fig. 2). It uses Intel’s 45-nm Hi-K metal-gate silicon technology on the 567-mm2 chip.
The experimental many-core SCC combines two processor cores with a router that has 384 kbytes of shared memory into a node that provides communication between all processors in a 2D mesh that has a 256-Gbyte/s bisection bandwidth. The mesh also provides access to four DDR3 memory controllers with up to 64 Gbytes of storage. The mesh switching system supplies low-level hardware acceleration.
Each core has its own L1 and L2 caches. Page-level cache coherency is managed via software. This allows experimentation with a range of communication methodologies, including message-passing, shared virtual memory, map-reduce, and actors. The nodes and memory controller are grouped for power management providing fine-grain control with a power envelope between 25 and 125 W.
Intel isn’t the only company working with many-core chips. Tilera is already delivering 64-core chips. In 2010, it plans a 100-core chip, the Tile-GX100, with a 64-bit processor architecture (Fig. 3). It offers hardware-based, multi-partition cache-coherent islands via its multilane mesh network.

These islands provide isolated compute regions that can run different applications and operating systems in a symmetric multiprocessing (SMP) fashion. It also supports Zero-Overhead Linux (ZOL), a “tickless kernel” feature that eliminates timer ticks and other Linux overhead from real-time applications. It can significantly improve real-time responsiveness and determinacy—and it’s available now.
The cloud isn’t the only place multicore will be hot. DSPs are lining up cores just as fast. Freescale’s MSC8156 is a six-core DSP based on the SC3850 StarCore architecture. Each core’s subsystems run at speeds up to 1 GHz, delivering 8000 million multiply accumulates per second (MMACS) per core or up to 48,000 MMACS per device.
Texas Instruments puts six 500-MHz C64x+ DSP cores on a chip found on the TMDXEVM6472, a MicroTCA-based evaluation board for the TMS320C6472 (Fig. 4). The chip uses 40% less power and 80% less board space than its predecessor. It also uses DDR2 memory and supports Gigabit Ethernet, Serial RapidIO, Utopia II, HPI, and TSIP with its EDMA switch fabric engine.
Four- and six-core AMD Opterons and Intel Xeons were the norm for 2009. Now, double the cores for 2010 and push the power envelope down for the quads. Intel’s quad-core Jasper Forest Xeon targets storage and communication applications. Support for non-transparent PCI Express bridging and hardware redundant array of independent disks (RAID) acceleration will make it ideal for redundant storage configurations. A single-core version squeaks in under 23 W.
Look for major competition and releases in the low end of the x86 spectrum. Intel’s Atom has been a great success, and new versions using fewer chips with smaller dies will be available later in the year. AMD and VIA Technologies look to carve out a chunk of this area. The superscalar, 64-bit Nano from VIA Technologies will add a little spice to this mix.
Multicore is also in the mix for the high end of MIPS and ARM architectures. Even the ARM Cortex-A5 has an architecture built around four cores. A sizable chunk of these higher-end chips will be coupled with coprocessors and multimedia acceleration hardware.
The number of applications that can take advantage of the other multicore platform, the GPU, is increasing rapidly. The use of the Khronos OpenCL (Open Computing Language) framework is providing a more level playing field, enabling applications to span even heterogeneous many-core environments. Arrays of GPUs are common and will be more so in 2010 as programmers recognize the kinds of applications that fit this mold. GPUs have 10 to 100 times as many cores compared to multicore chips with more complex cores.
Probably more important this year is the recognition that a single GPU can do double duty as a compute and display engine. This is especially important as GPUs are being paired with CPUs on mobile multimedia platforms. 

The 8- and 16-bit micros will get significantly more pressure from their 32-bit cousins. Cortex-M0 and Cortex-M3 incarnations broke the $1 barrier ages ago and are pushing the power-consumption envelope that matches or is below that of many 8- and 16-bit competitors. Development kits for the Cortex-M0 like IAR’s KickStart kit for the NXP LPC1114 will hit the market early this year (Fig. 5).
Developers are going to have even bigger challenges trying to decide what platform to use as the number of microcontroller options continues to grow. Issues such as instruction set efficiency now come into play. For example, a 32-bit processor may handle applications that are awake for a short period of time more efficiently, allowing it to get the job done more quickly. But speed is only one aspect. Startup and shutdown costs also affect power consumption, and not all designs are created equally.
Look for more DDR2 support moving up the food chain in lieu of SDRAM. Atmel’s SAM9M10 ARM926-based microcontroller is a good example. It even has dual external buses that enable it to handle scenarios such as dedicating peripherals and memory to their own bus.

FPGAs will continue their push into spaces once reserved for ASICs and off-the-shelf micros. Flash-based FPGAs like Actel’s low-cost Igloo and ProASIC3 and Lattice Semiconductor LatticeXP2 line deliver single-chip solutions that use less power than ever before, providing significantly more flexibility than micros. They can also address long-term issues such as intellectual property (IP) control.

Support and development tools remain a major issue, but improvements last year and the expected improvements in 2010 bode well for designers looking to make the FPGA plunge. Development kits like Altium’s NanoBoard 3000 target specific application areas and streamline development chores, permitting even FPGA novices to turn around designs quickly (Fig. 6).
Multicore is at home on FPGAs. Soft cores like Altera’s 32-bit NIOS II work nicely with Altera’s Stratix IV, which also supports PCI Express Gen 2. The agreement that Xilinx and ARM signed in 2009 should prove to be interesting in 2010, with ARM hard cores likely to join PowerPC-based FPGAs. ARM already has the Cortex-M1 soft core available for any FPGA platform.
Cypress Semiconductor’s 8051 PSoC 3 and ARM-based PSoC 5 announcement in 2009 was an interesting turn given the flexibility of their soft peripherals. The peripherals aren’t implemented as an FPGA, but they are close and significantly more flexible than most alternatives. This year should see developers working to master the use of Verilog to define new peripherals.
Likewise, Atmel’s CAP will garner new interest as more customers let Atmel tell the world about their solutions. CAP wraps an FPGA around an ARM core in Atmel’s development kit. Designs are then turned into ASICs for a fraction of the cost of a fully custom ASIC.

DDR3 will remain the mainstay at the high end and for PC-class products for a couple more years. As noted, DDR2 will infiltrate the microcontroller realm. DDR4 is still a light in the 2012 time frame.
Nonvolatile storage will be a bit more interesting in 2010. NAND and NOR flash will maintain the bulk of shipments. Multi-level cell (MLC) flash will continue to deliver higher capacity with more attention paid to long-term reliability, especially in the enterprise. FRAM, MRAM, and phase change memory will see much more use, though they are starting from a much smaller market percentage. They will still be primarily in niche areas, but movement toward more mainstream use will occur in 2010.

It’s time for the third generation of high-speed serial interfaces to make a dent in product shipments. Actually, it has happened already for technologies such as Serial RapidIO and InfiniBand, which began shipping third-generation products in 2009. Faster versions are on the drawing board, and some will see the light of day in 2010.
The bigger change will be with USB 3.0, SATA-III, and PCI Express because of their impact on PCs and servers (Fig. 7). Of these, USB 3.0, or SuperSpeed USB, will likely have the biggest impact in the long run. Its 4.8-Gbit/s rate will be needed for external flash and hard-drive storage, and it is also sufficient bandwidth for streaming HD video content. 

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