Get the Timing Right for Next-gen Subsystems

The latest in low-jitter clocking devices brings flexibility to, and lowers the BOM for, timing subsystems.

Innovations in deep submicron CMOS technology has fostered a new breed of highly integrated, low-jitter clocking devices that help address the increasing complexity of timing subsystems. Such subsystems are found in equipment ranging from next-generation networking and telecommunications, to next-gen test-andmeasurement and video broadcast equipment.

Often, next-generation equipment is being designed so that it can be reconfigured to address a broader range of end applications or communication standards. One example of this can be seen in production video systems, in which a common platform must be reconfigured to create video content that meets the local standards of various countries or regions. Another example is multi-service networking equipment that has to deliver the flexibility to support a wide range of network different traffic types, such as 10Gbps SONET/SDH, 10GbE, and 10Gbps Fibre Channel.

Obviously, one needs to support this need for enhanced flexibility. Thus, the timing subsystem must be adapted to support system clock generation over a much wider range of frequencies than was previously required.


Traditional high-performance, timing subsystem implementations are built around fixed-frequency phase-locked loops (PLLs), which aren't easily scaled to support multi-frequency operation. This lack of flexibility was ripe for innovation, given the capabilities of digital signal processing (DSP) and mixed-signal circuits realised in fine-line CMOS process technologies. Previously, low-jitter timing subsystems were constructed using many discrete high-performance components, a complex board layout providing noise isolation, and extensive phase-locked loop expertise, which can be very difficult to find or cultivate. The custom-built PLLs used to build the timing subsystems were based on expensive, high-performance, low jitter voltage-controlled crystal oscillators (VCXOs) or voltage-controlled SAW oscillators (VCSOs).

However, the traditional approach to implementing the timing subsystem isn't easily reconfigurable to support different non-integer related frequencies, due to the fixed-frequency nature of VCXOs and VCSOs. At best, a PLL architecture based on a collection of different frequency VCXOs or VCSOs would have to be used to satisfy multi-frequency operation. The obvious drawbacks to this approach include additional board space, design time, design risk, cost, and bill-ofmaterials (BOM) management.


To address the need for high performance, a high level of integration, and multi-frequency operation, Silicon Labs' recently launched the Si53xx Any-Rate Precision Clocks product family. This family of nine devices uses the company's DSPLL technology to offer reconfigurable, frequency- agile precision clock multipliers and jitter attenuators (Fig. 1).

DSPLL, in its third generation, offers an IC-based solution that has equivalent performance to the discretely built PLL implementations using expensive VCXOs or VCSOs, and provides the reconfigurable frequency agility lacking in discrete PLL designs.

For example, the Si53xx family can generate any output frequencies from 2kHz to 945MHz and select frequencies to 1.4GHz from any input frequency between 2kHz and 710MHz. Frequency agility allows one Si53xx IC to replace multiple, different, discretely implemented PLLs or complex multi-VCXObased PLLs designed to support operation at multiple frequencies. The benefit to the customer is reduced cost, board space, BOM, and design time and risk.


By employing DSPLL technology, the Si53xx family can integrate all of the discrete components traditionally used to implement a PLL into a single CMOS IC. This approach eliminates all of the noise entry points between each circuit element found in discretely implemented PLLs, including but not limited to the input multiplexer, VCSO, loop filter components, phase detector, and output buffer. As a result, the Si53xx family helps simplify the task of achieving ultra-low-jitter performance as low as 0.3ps RMS by providing much greater immunity to system- level noise sources.

To provide both a high-performance and full-featured solution, the Si53xx family also offers an integrated loop filter with selectable bandwidths. This feature enables designers to alter the loop bandwidth without changing components and enabling jitter performance optimisation at the application level. In addition, the Si53xx devices support up to four clock inputs and five differential clock outputs, eliminating the need for external multiplexers and fanout buffers traditionally found in today's complex timing subsystems (Fig. 2).

The precision clocks also help simplify the design and supplychain issues of modern timing architectures. By completely integrating a frequency reconfigurable PLL into the Si53xx family, the design time associated with implementing individual PLLs can be saved. As a result, the PLL designer is free to address other more important design issues.

The devices can be reused many times within a system to eliminate multiple different timing PLL implementations and their associated VCXOs, VCSOs, and other miscellaneous BOM. This avoids the cost of inventory and supply-chain headaches associated with highperformance discretely implemented VCXO- and VCSObased timing PLLs. In addition, the Si53xx family uses high-volume standard IC manufacturing technology, which can reduce lead times to four weeks compared with the long, unpredictable lead times associated with VCXOs and VCSOs.


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