Engineers designing pc-board power-distribution systems begin by dividing the design into four parts: the power source (battery, converter, or regulator), the pc board, a board decoupling capacitor, and a chip decoupling capacitor. This article focuses on the second and fourth items. Generally, the board decoupling capacitor is large, about 10 mF or greater, and designed for use in special cases.

Designing in a decoupling capacitor is a two-step process. First, calculate the capacitor value as determined by the electrical requirements. Then, place the part on the pc board. Specifically, how far from the digital chip can a capacitor be placed? Often the pc board itself is overlooked as part of the decoupling design. This article ex-plains where the board fits into the decoupling design process.

The Need For Decoupling: Basically, a power source supplies digital chips with energy via a conductor that links the two. This source may be located "far" from the chip. Designs with 5 in. of 16-AWG wire and 4 in. of 20-mil trace aren't rare. The conductors have resistance, capacitance, and inductance that affect the quality of the energy delivered to the part. The last item, the inductance, is proportional to the conductor's length and causes the most quality problems.

Of critical concern is the layout because it determines the total inductance and the loop area around which current flows. This loop area can, and probably will, radiate electromagnetic interference (EMI).

Placing a small power supply (like a capacitor) next to the chips minimizes the trace length from the capacitor to the chips' V_{cc} pin and back, shrinking the current's loop area. This in turn minimizes the voltage drop problem caused by the inductance in the conductors. Because the loop area is minimized, EMI also is reduced.

Connecting a digital chip, U1, directly to the supply means dealing with perhaps several inches of trace. Instead, capacitor C1, with its parasitic elements, L2 and R2, is inserted in the circuit "close" to the chip, less than an inch away *(Fig. 1)*. Element L3 is the wiring inductance between C1 and U1. L1 and R1 are the parasitic elements of the conductor from the power supply to the capacitor.

Now the trace length is reduced to mils, and line impedance is reduced as much as practicable. C2, a key player here, determines how much current must be supplied from the power supply. This part represents U1's internal load and the external loads U1 must drive. When S1 closes, these loads are connected to the power supply, and they all demand current immediately.

Note that inductance is the primary contributor to the impedance between the power supply and the switch. For example, the resistance, capacitance, and inductance for a 10-mil wide trace are about 0.02 Ω/in., 2 pF/in., and 20 nH/in., respectively. These are typical numbers for most traces (microstrip and stripline) and wiring used in manufacturing pc boards. Above about 100 kHz, the inductive impedance, jΩl, is the dominant impedance.

Therefore, adding C1 accomplishes two things. It reduces the wiring inductance between the chip and the source of power necessary during switching. This prevents V1, the V_{cc} voltage to U1, from going below the value needed for proper circuit operation. Moreover, it reduces the loop area that the high-frequency currents flow around and the resulting EMI.

So, the capacitor keeps V1 up, but how high is necessary? This concern focuses chiefly on a part's noise margin, i.e., the minimum voltage noise margin, V_{NMmin}, that can exist and still allow proper circuit operation. (This can be a little tricky to compute because the actual value depends on the semiconductor's noise margin. That somewhat depends proportionally on the power-supply voltage.) From Figure 1, proper operation means fulfilling the condition:

V_{NMmin}≥ VPS — V_{Zmax}(1)

In this illustration, V_{Zmax} is dropped wholly across L3.

The current, I, also needs to be examined. Simply stated, this is the current requested by the digital inputs, and the designer must ensure its supply. Because this is the maximum current required, it's labeled I_{max}. Therefore, the maximum impedance, Z_{max}, between the power supply and the switch can be no more than:

|Z_{max}| ≥ (V_{Zmax}/I_{max}) (2)

Recall that the trace length from source to chip was 5 in. of 16-AWG wire and 4 in. of 20-mil trace, yielding about 100 nH of inductance. At some frequency, f, the inductive impedance will be greater than the allowed Z_{max} that can be tolerated. This frequency is found by shuffling the equation for an inductor's impedance to give:

f_{max}= |Z_{max}|/2πL (3)

Above this frequency, C1 can't provide enough voltage to meet the part's required noise margins, and information can't be successfully transmitted.

Sizing The Capacitor: The decoupling capacitor supplies the "high-frequency" currents to the chips on the pc board, while the power source provides the "low-frequency" current. To determine the capacitor's size, start by assembling the information needed to calculate f_{max}, at which the currents from the power source begin to fall off. These are the "low-frequency" currents. Also needed is the required current to U1's loads, the voltage necessary to successfully operate the parts, and the switching time.

To obtain these quantities, consider a capacitor's parasitic elements. For a brief period after switching occurs, the primary power source for U1 is the decoupling capacitor, along with its parasitic elements--the equivalent series resistance (ESR) and equivalent series inductance (ESL). The ESL contains two components: the conductor's inductance, which the designer tries to minimize, and the capacitor's inductance, which the designer lives with.

To size the decoupling capacitor, first determine the number, N, and size of the capacitive loads U1 must drive. This number, along with the capacitive input value to the next chip (U2), and the change in voltage over time determine the maximum current needed. The current is found using the familiar formula I = C Χ (dV/dt). In this example, it is:

Delta V is the worst-case change in the voltage during the switching, 0 V to V_{PS}. Take care to use the correct voltage when implementing mixed-voltage parts, say, 3.3 V/5 V.

Delta t is the rise time of the pulse switching of logic device U1. Because rise times are calculated in a number of ways, use the one that gives worst-case rise time, or the fastest. Now, the current pulled by the load must come from the decoupling capacitor, so find the capacitor value with:

C = I/(dV/dt) (5)

Although we have now determined the decoupling capacitor's value, we haven't completed the design.

Placing The Capacitor: Next, the designer must determine where on the board to place the capacitor. It should be located so as to minimize the trace inductance between the capacitor and the chip. Note that the inductance should be minimized, not the trace length. Minimizing the inductance, rather than the trace length, allows more design freedom when placing the capacitors on the board. First, the designer should determine the maximum useable trace length to maintain the most design freedom.

The procedure is as follows: The designer needs a capacitor(s) to work from f_{max }*(Equation 3)* to some upper frequency. Determining that upper frequency takes an understanding of the ideal digital waveform output and the necessity to keep that shape to some degree. This is a small part of signal-integrity design.

The ideal digital circuit transmits a square pulse to the next circuit. In the real world, a square pulse can't be achieved, but a trapezoidal pulse can. Examining the Fourier series of the latter pulse shows the fundamental frequency at which the trapezoidal pulse is generated along with all of its harmonics. Of course, when adding them all together, the original trapezoidal pulse is restored.

But what if all of the harmonics weren't added back? What if just the first five or 10 harmonics were added? Would there be enough harmonics to make a "trapezoidal" pulse that would fool the input circuits? It turns out that in most cases, adding only the first 10 harmonics restores enough of the original waveform to fool most circuits, most of the time. This determines the upper frequency that must be dealt with when designing the decoupling capacitor, i.e., 10 3 fpulse. (Another method suggested to determine the upper frequency is using f = 1/πt_{r}, where t_{r} is the pulse rise time. At this frequency, the harmonic energy content is very small and it rolls off at —40 dB/decade.)

Now it's possible to start designing by determining the worst-case tolerable change in the power-supply voltage. For CMOS, this figure is the noise margin V_{OH} — V_{IH} (see a data sheet for these values). The worst-case change is:

V = V_{CC}(nominal) — (V_{OH}+10% Χ V_{CC}) (6)

The 10% multiplier is a power-supply derating factor.

Using Equation 6 and the relationship of voltage to an inductor's change in current, determine the maximum allowable inductance, L:

L = V/(dI/dt) (7)

Again, L is the total series inductance: capacitor, trace, the chip's bond wire and leads, etc.; dI is the maximum change in current; and dt is the current's rise time.

*Trace Length*: For two or more capacitors, with different trace lengths connected in parallel to the power input of a chip, the effective trace length determines how far from the chip the capacitors may be placed. Recall that trace length is directly related to the inductance of traces. Thus, the effective trace length is found through the formula for inductors in parallel, and the equivalent trace length, l_{E}, is:

l_{E}= (l_{1 }Χ l_{2})/(l_{1}+ l_{2}) (8)

with l_{1} and l_{2} being the trace lengths of the parallel capacitors. The maximum distance either parallel capacitor can be from the V_{cc} pin is l_{E}.

Now comes the final consideration. Once the capacitor is selected and placed on the pc board, check where the resonant frequency of the capacitor and the parasitic inductance occurs. This can be found from:

f = 1/2π = π √—LC (9)

where L = L_{ESL}+ L_{TRACE}.

Above this frequency, the capacitor is rapidly becoming an inductor. If the resonant frequency occurs at too low a frequency compared to 10 * fpulse, the design needs to be examined to determine what compromises to make.

Using Multiple Decoupling Capacitors: If N capacitors of equal value are used, the overall ESL and ESR are slashed by 1/N *(Fig. 2)*. This is a special case when the traces connecting the capacitors between power and ground are equal. It also is assumed that the mutual coupling between the inductors is very small. The impedance curve of N capacitors of the same value approximates the curve of a single capacitor.

If N capacitors of different values are implemented, the ESR and ESL are reduced. However, this introduces a resonant peak in the impedance curve that might have serious consequences for the design *(Fig. 3)*. Again, it's assumed that the trace lengths are equal.

Use The PC Board: Don't forget about the pc board. Ignoring the advantages that it provides, almost free of charge, can drive up the design cost by requiring additional parts. These parts take up extra space, decrease the overall reliability, and possibly increase EMI.

Equation 10 shows the formula for the impedance of a set of parallel planes *(see the Equation Listing)*. This is simply the formula for the impedance of series LRC circuits. This formula is usable as long as the pc board doesn't start to behave like a transmission line. In other words, it's usable if l < λ/20, where l is the greatest dimension of the pc board (the diagonal), and * is the wavelength associated with the upper frequency.

Up until this point, the board impedance is mostly capacitive and the board can supply all required currents above the cutoff frequency of the decoupling capacitor. Because the ESR is very, very small, and the parasitic inductance is also very small, a pc board will exhibit a very low impedance over a wide range of frequencies.

A pc board with two adjacent planes devoted to power and ground has an excellent capacitor inherent in that design. The formula for a parallel plate capacitor determines the pc board's capacitance:

C (pF) = ε(A/d) = 0.225(ε_{r}/d)A (11)

(the last part of the equation is applicable when working in inches) where: ε = ε_{0 }Χ ε_{r}, ε_{0} is the permitivity of free space, 8.85 pF/m, and e_{r} is the relative dielectric constant of the material between the plates. For FR4 the number is about 4.5, A is the area between the plates, and d is the separation of the plates.

Effectively, there is no upper frequency limitation to a pc board's ability to supply current to the V_{cc} pin. (Note that the author is taking some liberty here. The design of pc boards is a complex issue with many dielectrics available to increase the upper frequency limit. For FR4, the upper frequency range is very high, greater than 2 GHz, which makes most of today's pc-board circuits for automotive products look as though the upper frequency were infinite. Realistically, the upper frequency is determined by the ratio of a board's maximum dimension, l, to the smallest wavelength, λ. This must be dealt with on the board, as long as the dimensions are electrically small.)

Unfortunately, the general capacitance value of a pc board in an automotive design is small. Typically, it's about 53 pF/in.^{2} with FR4 as the dielectric, a plate-to-plate separation of 20 mils, and solid power and ground planes. When talking about four-layer FR4 pc boards, remember that they will have a range of dielectric thicknesses. The variation can come from manufacturing variability, required thickness of the overall board, required flexibility or stiffness, copper thickness (which might influence the dielectric thickness), and breakdown voltage requirements. Variation for a typical board with no special requirements can range from 20 to 30 mils (0.5 to 0.8 mm).

The quality of the pc-board capacitor is usually described as excellent because there's little inductance. As mentioned previously, inductance is the main reason for a capacitor's degradation as frequency increases.

The small size of the capacitance is a cause for concern. A general capacitance value quoted for a board to be effective in supplying currents is greater than 500 pF/in.2 Achieving such values isn't possible with FR4 boards. Values in that range require specialized pc-board design and materials.

EMC Benefits: Apart from the signal-integrity benefits achieved from a well-designed power-distribution system, the pc board will also have lower EMI. As mentioned earlier, this is primarily due to the decrease in the loop area. This appears in two ways. First, Faraday's Law shows the effect that loop area, A, has on voltages induced into the circuit by currents flowing in other circuits:

V_{INDUCED}(volts) = \[(µAN/2πd\] Χ (dI/dt) Χ cos(θ) (12)

Also, a simplified expression of the electromagnetic fields from the current loops in the digital circuit shows a much lower set of emissions for the circuit with the smaller loop:

E (V/m) = 263 Χ 10^{-}^{16 }Χ \[f^{2}A(I/r)\] (13)

Cost Benefits: A well-designed power-distribution system can save a lot of money. Equation 14 is a simple formula proving the savings as a function of a parts count reduction *(see the Equation Listing)*. For example, consider a pc-board design that eliminates five capacitors on 400,000 boards, built each year for two years. Assume that it costs $0.006 to place each capacitor on the board. The net savings is about $36,000.

Thus far the discussion has centered around supplying currents to the chips. But the designer may want to limit current to the chips also. Remember that a chip can operate perfectly well as long as it receives the current it needs below an upper frequency, 10 * f_{max}, or 1/πt_{r}. The designer can't touch any of the currents in those frequencies. But above some upper frequency, the chip can operate perfectly well without the currents. Moreover, because those currents might be generating EMI, they can be suppressed, yielding a reduction in EMI.

To limit the currents, insert a ferrite(s) between the decoupling capacitor and the chip's V_{cc} line(s). Before doing so, though, designers must know that they won't be current-starving the chip. It's always a good idea to tell the chip manufacturer what's intended and get its approval to place the ferrite.