ISP Configuration PROM Offers Parallel Loading

A family of in-system programmable (ISP) serial/parallel-load flash CPLD/FPGA configuration PROMs, the XC1800 Series configuration memories are used for the logic initialization of any SRAM-based CPLD such as the Xilinx CoolRunner series or FPGAs. Ranging from 128 Kb to 4 Mb of configuration memory, the devices can dramatically increase the range of programmable logic device densities that can be served by a single configuration chip while maintaining ease-of-use. Unlike many configuration PROMs, the entire XC1800 family can be re-programmed in-system to accommodate late changes and remote configuration without replacing or removing PROMs from the system. This ISP feature uses IEEE 1149.1 Boundary Scan (JTAG) circuits that let the XC1800 devices be integrated into the host system's JTAG chain to reduce testing and programming overhead. The Boundary Scan capability allows functional testing of the entire system board to expedite board-level testing. The XC1800 Series operates from 3.3V and the I/O pins accept 5V, 3.3V and 2.5V signals while driving 3.3V or 2.5V output signals. Device packaging ranges from 20-pin PLCC to 44-pin VQFP.