Electronic Design

Jumbo Digital Chips Bank On A "Small" Future

Two-billion-transistor processors and four-billion-transistor memories, with process rules dropping to 65 nm and 45 nm, shake up digital technology.

Smaller is better—that's the ongoing mantra within the digital spectrum. At least that's the case for transistors, which are getting mighty small indeed.

Today's best production processes are based on 90-nm features. But companies are already working on device structures that will enable manufacturing flows based on 65- and then 45-nm design rules. Yet such small features create a host of challenges like lithography, device structures, leakage currents, and device isolation.

While researchers work on the fabrication challenges, architects are trying to figure out what to build with all of the transistors that can be integrated on one chip. Over the last decade, integratable transistors have increased by almost two orders of magnitude, from about 60 million to almost 2 billion for processors and to over 4 billion transistors for the most advanced memories (see the figure).

Thanks to the high area efficiency of storage cells in NAND flash memories, companies will demonstrate prototypes of next-generation devices that can store 8 Gbits on a single chip. To reach those lofty heights, vendors must integrate over 4 billion multilevel cells that store two bits per cell using processes based on features as small as 63 nm.

Novel nonvolatile memory technologies are also in the works to create the ideal memory chip—a device that permits unlimited reads and writes, offers fast and symmetrical read and write times, and consumes little power. Memories based on ferroelectric, magnetoresistive, and phase-change materials and even carbon nanotubes are all on the drawing boards. Ferroelectric devices are now in production, and samples of MRAMs are expected early this year.

First research prototypes of DDR2 memories with over 2 billion storage cells (one transistor/one capacitor per cell) will make their debut in the DRAM arena. Fabricated with 80-nm process rules, the 2-Gbit DRAM will deliver data at 800 Mbits/s per pin. Other anticipated developments include the first demonstrations of storage cells that do away with capacitors by leveraging the floating-body effect of partially depleted silicon-on-insulator (SOI). This approach promises to double the number of bits that can be integrated per square millimeter.

The ability to cram lots of memory onto a chip also helped processors boost performance. Level 1 data and instruction caches have been supplemented by a unified level 2 cache. Now level 3 caches can be integrated on-chip, too. In addition, multiple processor cores can merge onto a single chip, enabling the processor to handle multiple execution streams.

At next month's International Solid State Circuits Conference, Intel will disclose a CPU with the highest transistor count to date—a dual-core Itanium with over 26.5 Mbytes of on-chip cache memory. Total transistor count is 1.72 billion devices, of which only 64 million are used for the CPU logic. This chip begs the question if it is a "smart" memory chip or a processor with lots of cache.

The same ability to integrate multiple processor cores and lots of memory can translate into higher-performance DSP chips—chips that can deliver teraoperations per second for extreme graphics engines. Such engines can provide realistic graphics for workstations, game boxes, and other consumer applications.

FPGAs, cell-based ASICs, and structured and platform ASICs also will benefit from the increased integration and performance. At the high end of the FPGA market, devices with close to 5 million system gates and up to 10 Mbits of memory will enable designers to create system-level solutions on a single chip. That's always been true for full cell-based designs, but it's now even more so as chip densities stretch beyond 20 million gates.

Over 20 vendors offer structured and platform ASICs, filling the new middle ground between FPGAs and cell-based approaches. These chips deliver a lower-cost option to cell-based ASICs and large FPGAs. As a result, designers have a more cost-effective solution when their application's volume isn't high enough to justify a cell-based ASIC but is too high to permit the use of the large and expensive SRAM-based FPGAs.

Lower-density FPGAs also are taking a new path, finding homes in high-volume consumer products such as cell phones, set-top boxes, and flat-panel HDTV systems. Two factors make this possible. First, the latest fine-featured process technologies have created smaller chip areas. Second, streamlined architectures retain logic flexibility with fewer circuits, also helping to shrink the size of the chip.

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