Electronic Design

Low-Voltage Differential Signaling Scheme Delivers Roadmap To 6.4-GHz Data Rates

A novel signaling interface that delivers up to 8 bits per clock cycle promises to open the door to low-power, high-speed chip-to-chip or board-to-module data transfers. Created by Rambus Inc. of Mountain View, Calif., the Yellowstone signaling scheme transfers data at 3.2 GHz today and provides a roadmap to double that in the not too distant future.

Yellowstone can be integrated into memory chips, graphics controllers, microprocessors, network processors and other network support circuits, and many other application-specific circuits. It's available as a block of intellectual property.

The interface's performance is scalable with voltage and frequency. It permits system implementations that deliver memory bandwidths from 10 to 100 Gbytes/s. Also, it doesn't require complex multilayer pc boards--just a four-layer board. This will help designers keep system costs competitive with existing approaches.

To combine high-performance, low power, and simple system implementation, Rambus mixed three key approaches: an ultra-low-voltage differential signaling scheme for low power, an octal-data-rate (ODR) transfer scheme for high-data throughput, and a FlexPhase circuit technology that adjusts signal timing to keep board costs low. The basic differential signal is only 200 mV p-p and is centered around a 1.1-V reference level.

The small signal swing allows high-speed transitions without consuming a lot of power, permitting many differential interfaces to be integrated on a chip. Able to transfer data bidirectionally, the differential interface, known as differential Rambus signaling levels (DRSL), includes on-chip termination. This simplifies board design (see the figure).

To boost the data rate to 3.2 GHz, the ODR scheme starts with a 400-MHz system clock internally multiplied fourfold by an on-chip phase-locked loop. The data then transfers out of or into the chip on both the leading and trailing edges of the 1.6-GHz internal clock. This yields a 3.2-GHz data transfer rate. (See the sidebar under Forefront at www.elecdesign.com or go to www.rambus.com.)

Such high data transfer speeds typically require signal trace matching to ensure consistent timing. But FlexPhase eliminates the need to match signal propagation delays by electrically adjusting the delays in the signal paths. This also eliminates the need for strict pc-board timing constraints.

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