Memory Controller Pumps Up DRAM System Data Rates

Avoiding the need to change the native memory interface, a novel controller and buffering scheme pushes data-transfer rates for standard SDRAMs to 3.2 Gbits/s/pin and up to 12.8 Gbits/s/pin for first-generation double-data-rate (DDR) SDRAMs. A controller and multiplexer/demultiplexer buffer make up this two-chip solution.

Silicon Pipe's Chaniplexer chip set, targeted at desktop and server systems, can use standard dual inline-memory modules (DIMMs). For applications demanding higher performance, the company's Seriplexer requires a redesigned DIMM to achieve data rates of 24 Gbits/s per pin and beyond.

In a Chaniplexer system, a controller connects to the host processor or DRAM controller's address/data bus and converts the parallel data into multiple differential serial channels. The multiple channels are then connected to the multiplexer/demultiplexers, which are positioned between the DIMM connector and the differential signal traces (see the figure).

The differential signals are more immune to noise than standard parallel buses. This adds more flexibility in the pc-board layout with respect to the DRAMs' proximity to the memory controller. Though some pc-board modifications are required for the existing memory-controller data path, no changes are needed to the host processor or chip set, or to the memory DIMMs.

Based on the Grand Canyon differential signaling scheme, serial channels virtually eliminate signal disruptions between a memory controller and its memories. The serial channels can transfer bit streams at data rates starting at 3.2 Gbits/s and scaling up to 8 Gbits/s and beyond, depending on the memory interface. When used with existing DIMMs and system logic, the Chaniplexer can implement systems with word widths of up to 128 bits and support as many as 32 DIMMs. When used with DDR DIMMs, data rates start at 12.8 Gbits/s and can scale to over 20 Gbits/s.

The Seriplexer scheme requires custom DIMMs optimized for the approach. With it, data transfers should hit 24 Gbits/s and higher. Silicon Pipe says that the Seriplexer has virtually no scaling limits, so it can work in systems that concurrently employ different memory technologies.