Electronic Design

Memory Front And Center

Intel keeps the processor chips simpler by leaving the memory and I/O interface chores to a central memory host controller (MHC). This has some advantages, including different system support using a common set of processor chips. Even so, Intel and AMD have distinct families for single-chip and mobile solutions. Intel's Xeon has larger caches and faster I/O than its Core 2 line, in addition to external cache support.

This approach doesn't dictate a single chip for the MHC. The current crop from Intel targets two-chip solutions. This may not appear as scalable as AMD's HyperTransport approach, but it is actually a factor of the MHC design, which is open-ended. There's no reason a HyperTransport-like approach or crossbar-switch approach couldn't be used instead.

A possible limiting factor is the interface between the processor chip and the MHC. This parallel front-side bus (FSB) is wide, making the MHC a very high-pin-count device. Pin count and board circuit-routing are major issues in system design, making systems with a large number of Intel processor chips very challenging.

See Associated Figure

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.