Memory Test and Programming Via Boundary Scan

Unlock the true potential of boundary-scan testing through various methods.

Accessing memory devices via the integral boundary-scan logic of IEEE-STD 1149.1 was first proposed in an ITC white paper titled “Memory Interconnection Test at Board Level,” authored by engineers at Philips Research Laboratories in 1992.

Over time, commercial boundary- scan solutions providers have offered software tools to automate the process and elevate the test coverage of digital circuits. The tools evolved from just boundary scan to boundary-scan devices to boundary-scan memory “clusters.” Indeed, as long ago as 1995, JTAG Technologies introduced the first board-level, automatic test program generator (ATPG) for accessing memory clusters via boundary scan (see the figure).

However, accessing memory via boundary scan is perceived as being relatively slow when compared to “mission-mode” operation. Accordingly, the testvector set must be defined to check principally for “manufacturing errors” (i.e., opens and shorts) rather than exhaustive patterns testing, which is meant to check the full accessing of all locations. Even so, this isn’t always critical since the silicon vendors will generally perform pattern sensitivity testing. On top of that, a full-functional test of the memory devices can be performed post PCB manufacture.

Today, the variety and complexity of memories that require testing in-situ has increased from simple SRAMs, DPRAMs, and DRAMs, to SSRAMs and SDRAMs, and now even DDRSDRAMs. However, satisfying the refresh times of fast devices and initialising the Write State Machine (WSM) has turned into a difficult and escalating challenge. That’s due to the time it takes to “line up” and then change patterns on device control pins (such as Clock, Clock Enable, Write Enable, and Output Enable). Whilst this is still feasible for current technologies, other emerging methods have been developed to safeguard testing in the future. Two examples of these methods are:

  • Static component interconnect test technology (SCITT): SCITT sees the inclusion of XOR and/or XNOR gates in the memory device that bypass the core functionality to provide a form of loopback testing (see IEEE P1581 for further details).
  • Built-in self test (BIST) IP cores (e.g., Logicvision’s EMT-IC): Embedded into ASICs, these cores are obtained under license by ASIC manufacturers. They can provide real-time “at-speed” testing of memory devices.

Device programming

After test, the other compelling reason to access memory via boundary scan has to do with in-system device programming. Access falls into two distinct categories: direct and indirect.

Direct programming via boundary scan is an established principle. Intel introduced the first devices with this feature in the early 1990s, before its product line was sold to Altera. Since then, JTAG (IEEE 1149.1) has become the de facto physical access point for CPLDs and a number of serial-configuration PROMs from Altera, Cypress, Lattice and Xilinx.

Since 2001, a new unified standard for direct programming, called IEEE 1532, has been introduced. This was initially devised by a working party comprising members from the aforementioned device vendors and boundary-scan tools companies.

Indeed, it has become almost incumbent on tools suppliers to become expert in all areas of device and memory programming to deliver fully rounded solutions for test and device programming. In addition to 1532-compliant devices, parts such as TI’s MSP430, ST’s PSD series, and Freescale’s MPC5500 devices rely on proprietary solutions.

Indirect programming, on the other hand, is applicable to flash devices (NOR and NAND) as well as some serial memories (PROMs, EEPROMs, and MDOCs). Of these, perhaps the most challenging to address is NAND flash. It’s complicated by the fact that each device has a unique valid block mask. Few boundaryscan tool vendors can interface readily with NAND flash. Flash programming can be enhanced (sped up) in a number of ways:

  • Increase TCK to maximum and isolate boundary-scan “programming” from other devices that might have a lower verified TCK rate, which would “slug” the system (typically this will involve placing flash-critical devices in a separate scan chain)
  • Use a mechanism such as JTAG Technologies’ AutoWrite to pulse the flash WE signal and reduce the BSR shift overhead
  • Shorten the scan chain.

In addition, a more recent challenge has emerged in programming protocol-based serial PROMs based on I2C and SPI bus. However, thanks to the ingenuity of test engineers, PROMs also can be programmed by emulating the serial protocol via boundary-scan access. This effectively means creating a serial to parallel to serial conversion.

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