Electronic Design

A Move To Advanced Packaging For Glue Logic

Advanced packaging technology for logic functions has been ahead of demand for the past five years or so. For much of this period, customers seeking smaller packages for their logic gates have been limited to leaded package styles. These packages include industry standards such as the SOT23, SC70, US8, SOIC, TSSOP, and QVSOP, with I/O counts ranging from five to 80 leads. With each product revision, logic vendors have moved to a smaller package, but with only modest size reductions.

However, in the past year or so, logic suppliers have started to convert to the newer package technologies like the land grid array (LGA), the molded leadless package (MLP), the ball grid array (BGA), and wafer-level chipscale package (WCSP) or flip chip. Each of these advanced packages offers dramatic size reductions. An LGA-type chip-scale package such as MicroPak is 65% smaller than the SC70 that it's meant to replace.

To a large extent, the development of these newer packages is being influenced by growing demand for single and dual logic gates in packages with five, six, or eight terminals. These tiny packages enable designers to squeeze in a single gate, buffer, or inverter that enables the addition of an extra feature in small portable phones, cameras, notebooks, and PDAs. Customers are now starting to adopt these advanced packages.

But continued development and adoption of new logic packages is expected to accelerate as logic suppliers and their customers overcome various technical challenges. A great obstacle to flip-chip packaging is the customer's inability to deal with fine terminal pitches. Today, customers can readily place packages with pitches as low as 0.5 mm. But finer pitches result in lower manufacturing yields at board insertion.

Accordingly, LGA and flip-chip-packaged single-gate logic today is designed with 0.5-mm terminal spacing. Flip chips accomplish this by being fabricated four to five times larger than the actual logic circuitry, negating some of the packaging savings. Assuming that customers eventually implement high-yielding assembly for smaller pitches such as 0.3 mm (allowing lower-cost flip chips), there are still other reasons to consider using the packaged LGA rather than the nonpackaged flip chip. Particularly important is adhesion to the pc board over operating environments. For some applications, the LGA—with substrate and large contact pads separate from the chip—better provides the thermal and mechanical properties necessary.

Customers have been easily adapting their leaded attachment methods for the leadless MLP and LGA and other chipscale packages by adjusting their various solder processes. Meanwhile, suppliers are adopting new handling equipment to test parts at the strip or wafer level rather than individually. They're also learning to produce leadfree (Pb-free) packages that can survive higher board-assembly-processing temperatures. An ongoing goal is to achieve a level 1 rating for moisture sensitivity to eliminate the need for costly, dry bag storage.

Beyond these obstacles, the ever present challenge to logic suppliers is to engineer pricing parity and achieve a sales ramp that supports the ever decreasing cost targets, while reducing size. The smallest chips, packaged for reliability and the highest yields through customers' manufacturing processes, will be adopted and ramped up the soonest.

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