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Electronic Design

The Move To Serial Bus Interfaces Promises Pin-Count Reductions

It seems that no matter which system-design conference you attend, there will be a session or two on serial buses that promise to eradicate wide parallel buses and other interconnections. Such buses are commonly found on connector backplanes, as well as in high-wire-count cables that connect disk drives to motherboards, external peripherals to systems, and even large systems to each other. The objective is simple—reduce system cost and complexity.

Serial interfaces can do this by first reducing the pin count—in some cases by 16 to one or 32 down to two or four. Reduced pin counts allow simpler and lower-cost cables to be used. Chip packages also require fewer pins, simplifying pc-board layout. Replacing a 16-wire bus with one wire requires the single-wire bus to operate at a clock rate 16 times faster than the parallel bus. In previous-generation systems, achieving the higher clock rates was challenging because serial data rates of just a few hundred megahertz pushed the technology.

However, the latest CMOS processes with design features of 0.13 µm and smaller let designers implement high-speed serializer-deserializer (SERDES) interfaces that can transfer data at rates of several gigahertz. Within another year or so, 10-GHz serial data interfaces will be achievable. At such speeds, most serial interfaces use differential signaling, so two pins are required for each serial channel.

Often, designers will divide the parallel data path into 8-bit wide segments and assign each segment to one serial channel. Thus a 64-bit bus would transform into a 16-wire interface, saving 48 pins. If several wide interfaces are used in a system logic chip, that savings could be multiplied by three or four times. Replacing three such wide interfaces would save about 144 pins and probably a considerable amount of power as well, not to mention the simplified pc-board layout achieved by eliminating 144 traces.

The latest serial efforts are focusing on adding gigabit and faster serial channels on CompactPCI and even next-generation VME backplanes for industrial applications, as well as on replacing the popular hard-disk ATA cable in the PC with a simpler serial cable. In the PC, such a change provides two benefits to system manufacturers.

First, it should reduce system cost by reducing the connector size and the number of wires in the cable. Second, it could permit longer cables to be used. This would give the system designer more flexibility in physically positioning the disk drive in the cabinet.

There is still much work to be done to ensure that all this can take place. Careful attention must be paid to the design of the SERDES interface to ensure signal robustness in the face of unpredictable loading. Additionally, timing issues related to converting the parallel interface to serial and vice-versa must be carefully analyzed to ensure that no bits are lost and data stays synchronized. At such high data rates, crosstalk may also become an issue. The use of differential signaling and NRZ coding will minimize that issue for the serial channels, but nearby signal lines may be affected.

Furthermore, the design must consume little power. When operating at speeds of 1 GHz and higher, a typical SERDES may consume 80 to 100 mW. In the earlier example in which three 64-bit buses are converted into 24 differential serial interfaces, 80 mW times 24 turns out to be about 2 W. Such power levels may compromise the overall power budget for the chip. Designers must therefore focus on further lowering SERDES power consumption.

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