EE Product News

Multi-Speed Network Accelerator Offers Protocol Processing

The JT1001 is a single-chip Ethernet network accelerator that enables servers or workstations to interface seamlessly with 10-Mbps, 100-Mbps or 1000-Mbps networks. The device's integrated protocol processing functions give LAN equipment OEMs the ability to design network interface cards (NICs) and LAN-on-motherboard implementations that offer higher performance than was previously possible, it's claimed. In addition, the chip enables OEMs to offer their customers a clear migration path from 10/100-Mbps to 100/1000-Mbps Ethernet capability.Among the chip's benefits to system designers is its ability to offload the host CPU, which frees the processor to work on other tasks. Until now, designers were compelled to embed an additional processor on NICs. What's more, the JT1001 has a large, 96-kbyte FIFO buffer, which allows multiple packets to be loaded into the buffer and burst across the bus for maximum efficiency. The latter capability is particularly important at gigabit speeds, when packets arrive quickly and significant time can be wasted by unnecessary relinquishing of bus control. Called Propulsion technology, the chip's ability to burst packets of data across the PCI bus minimizes bus arbitration and is said to eliminate logical-to-physical address translation. It scales to wider bus widths and faster clock rates and also minimizes interrupts by coalescing transfers across the bus. The technology sidesteps earlier scatter-gather approaches that waste bus bandwidth and limit network performance.Ample design support is available in the form of certified device drivers, reference designs and sample boards. Detailed data sheets and application notes are also available, as well as licensable source code. JT1001 network accelerator IC is available now in sample quantities.


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