EE Product News

Multi-Tap Delay Line Simplifies Designs In Low-Power Digital Systems

Designers working with low voltages and small board spaces will benefit from the DS1100L 5-tap Solid-State Delay line, touted as the industry's first five-tap, solid-state delay line for 3V applications. Total delays offered are from 20 to 300 ns and tap-to-tap delays from 4 to 60 ns. As timing issues become critical in high-speed designs, the circuit contributes toward higher performance with higher precision, smaller size, and power savings.
Currently, boards in high-speed digital telecomm servers, routers and switches demand the most in precision timing, low voltage and small footprint. The chip uses 30% of the current and less than 20% of the energy and occupies less than 1/15 the space of 5V parts, it's claimed. Package options include an 8-pin DIP, 8-pin SOIC and 8-pin µSOP. Pricing is $2.72 each/1,000 in SOIC package.


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