Companies such as Rio Design Automation have made much lately about the need for chip designers to be more aware of the chip’s package constraints, and the message has been received. Chip designers are making a more conscious effort to close the gap between the design of high-performance chips and packages and the integration of those chips with the rest of the electronic system. This attention results in better-performing systems that are used in a variety of different applications.
The next order of business is to improve the chip’s relationship with the printed-circuit board (PCB), finding a way to improve I/O planning between the chip and the PCB. It would be most effective at the point where PCB design/planning determines the package’s interface to the board. (This was traditionally termed the package’s “pinout,” but today, “ballout” may be more accurate.)
An early I/O package plan would enable designers to analyze the entire interconnect, from the chip’s I/O buffers to the PCB. I/O planning reduces costs by discovering the minimum die size possible via optimized I/O and bump placement combined with a cost-effective package option. It includes synthesis, placement and routing, and the ability to analyze timing, power, and signal integrity.
These functions must work with industry-standard data files, such as DEF and LEF, and tool interfaces. To enable simultaneous representation of the entire chip, package, and PCB, the I/O planning environment needs a unified data model represented in a common database. Along with providing the basis for optimizing an initial I/O plan for the chip, it helps resolve I/O-related questions throughout the design flow.
At any point in the flow, chip designers can interactively view the effect of I/O changes to the chip’s floorplan. The methodology requires a user interface for collecting and managing I/O data in a bump/ball-grid array (BGA) map. In contrast to the error-prone task of entering and maintaining I/O data in a general-purpose spreadsheet, the I/O planning interface acts as a dynamic repository with the correct state of the I/O plan.
Constraints driving the fixed-ball plan are numerous and include PCB routing restrictions that minimize cost by minimizing layers. Component placement on the PCB determines which side of the package a high-speed bus needs to be located on and how that needs to be driven up to the chip. Electrical constraints, such as differential pairs, capturing those and honoring them in the chip/package co-design, need to be considered. So do power and ground planning.
Another area for consideration is PCB reuse, either as a complete reuse or a partial reuse where critical circuitry—radio frequency (RF), for example—or a high-speed interface such as DDR has already been characterized and validated. This will assist the designer who wants to fix the ball assignment to fit that predefined circuitry. One final area where I/O planning is needed is the ball out predefined by the designer.
I/O planning must be part of the overall system design flow. While chip designers need not become packaging or PCB experts, design guidance should be built into their design tools. By introducing automated I/O planning early in the design cycle, chip designers, working in concert with package and PCB engineers, will ensure good I/O performance.
Rio Design Automation Inc.
www.rio-da.com