Electronic Design

Network Processor Crafted For "The Last Mile"

A new family of multiservice network processors will enable the design of broadband customer-premise equipment (CPE). From Brecis Communications, the MSP5000 three-processor system will multiservice applications such as packetized voice and data with no loss in quality of service. Also in the works are the MSP-4000, -3000, and -2000.

"The MSP5000 is architected to tackle multiple, simultaneous streams of voice and data at the end of the last mile," notes George Apostol, director of engineering for system architecture and integration at Brecis. The open architecture is scalable to higher data rates and provides predictable latency and jitter characteristics to make the design robust.

The MSP5000 consists of a 200-MHz MIPS 32-bit RISC core for system management and traffic control, and two 160-MIPS ZSP400 DSP cores for voice and packet processing. Each DSP core is supported by a hardware accelerator. A proprietary 3.2-Gbit/s multiservice bus allows the three main processing engines to talk to each other, ensuring efficient peer-to-peer communications. This minimizes the risk of delay and jitter to voice payloads.

Other functions on-chip include dual 10/100 Ethernet MACs, a telephony voice interface, a wide-area network (WAN) data interface, a data-encryption-standard (DES) accelerator, packet authentication, a memory controller, external interfaces for configuring external devices, a JTAG interface for debugging, and a four-way data switch.

Together with the hardware accelerator, the voice engine supports up to 24 voice channels, in addition to echo cancellation, tone detection, and voice compression. The packet engine provides ATM and frame-relay encapsulation, packet classification, and shaping. The high-bandwidth multiservice bus is segmented and operates on a split-transaction protocol. It provides dynamic priority switching based on the classification of data types, as well as intelligent DMA capability. Connectivity to the bus is via data-transfer units.

Based on 0.18-µm CMOS, the MSP5000 consumes 2 W. It comes in a 369-ball plastic BGA. Slated for production in the fourth quarter, it costs less than $50.00 in volume quantities. It's also backed by a full suite of development tools and a complete development program that features evaluation boards, software, application engineering support, training, and documentation. And, it will provide APIs to support RTOSs including VxWorks, Linux, and BSD. Designed for limited-voice and data applications, the MSP4000/3000/2000 derivatives will sample in the fourth quarter.

Brecis Communications, 2025 Gateway Place, Suite 132, San Jose, CA 95110; (408) 437-9900; fax (408) 437-9099; www.brecis.com.

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