EE Product News

New Packaging Down-Sizes Logic Devices

An alliance between Philips Semiconductors and Fairchild Semiconductor has led to the development of smaller-scale packaging for the two companies’ logic devices. Addressing the ongoing demand for smaller components to free-up board space for additional devices or to shrink board size to permit further miniaturization of end-products, Philips’s lead-free, very-thin Depopulated Quad Flat-pack No-leads (DQFN) packages are about 75% smaller than TSSOPs. The DQFN package comes in 14-, 16- and 20-pin configurations, with 14-pin devices having a 2.5 x 3 mm footprint. DQFNs also incorporate an exposed die paddle that helps improve heat dissipation by some 20% compared to TSSOPs. And by eliminating leads, DQFNs are also said to eliminate coplanarity and bent lead problems. In addition to a footprint of only 1.45 x 1.00 mm and a height of just 0.55 mm, Fairchild’s 6-terminal MicroPak also features leadless contact pads that are said to eliminate the potential loss of coplanarity during the production process. They also allow the package to be soldered to boards more efficiently. Among the parts to be housed in DQFNs are standard logic gates and octals, while MicroPaks will house, among other things, single- and dual-gate devices. Fairchild and Philips will act as alternate sources for each other’s parts and are working to make the packages industry standards. For more details, contact Cliff Lloyd at PHILIPS SEMICONDUCTORS, Logic Products Group, Sunnyvale, CA. (408) 991-4764. Richard Lewis at FAIRCHILD SEMICONDUCTOR, Interface and Logic Group, South Portland, ME. (207) 775-8797.


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