Electronic Design

Optimize Power Distribution Analysis In High-Speed System Designs

With operating voltages falling and operating frequencies rising, frequency-domain analysis is essential.

Modern, high-speed system behavior is critically dependent on power-distribution-system (PDS) designs that deliver power well beyond 400 MHz. PDS design, however, has become too complex to do by hand. Often, this results in a PDS that's either under-designed (with excessive radiated EMI and stability problems) or over-designed (driving up system cost and complexity).

By developing a design-and-analysis strategy that looks at PDS behavior in the frequency domain, designers can ensure that their PDS implementations are both reliable and cost-efficient.

Over the past five years, the use of signal-integrity (SI) tools to predict digital switching behavior has moved from the domain of the SI guru to the desk of the mainstream design engineer. SI tools have proven valuable in identifying high-speed SI and crosstalk problems. They have also assisted in developing placement/routing strategies than can be used to minimize the chance of speed-related problems after pc-board layout.

Like all computer modeling tools, SI simulators are only as good as the data fed to them. And because SI simulation is a form of analog analysis, there will always be a margin of error involved. In fact, no two analog simulators will deliver exactly the same answer, even with the same models and the same set of input conditions. There simply are no definite answers in an analog world. The accuracy of analog analysis is based on the elements used to model the circuit and how well they represent the device's real-world behavior. That's why understanding which physical effects are modeled and what conclusions can be drawn from the simulation results are the keys to the successful use of SI tools.

All simulators make some idealized assumptions about circuit behavior simply because no simulator can model every possible physical effect. For example, there are several ways to model a length of a pc-board interconnect trace. Simple models represent only the trace characteristic impedance (Z0) and delay. Such models are said to be ideal or lossless transmission line models. A lossless trace model is usually suitable for traces with data rates under 50 million transfers/s (MT/s) and less than 12 in. long. The next level of transmission-line modeling includes the trace dc series resistance, which increases with trace length.

Since a pc-board trace isn't an ideal conductor, it exhibits a linear resistance of approximately several ohms per foot. Accurate modeling of trace dc resistance becomes important if the trace is long or the circuit is sensitive to small amounts of resistance. In high-frequency circuits, the "skin-effect" phenomenon causes high-frequency currents to concentrate along the surfaces of the trace, instead of being distributed uniformly across the cross section. Because higher frequencies constrict current to flow in a diminished cross-sectional area, trace resistance per-unit length increases with frequency. That's why for SI analysis above 200 MHz, accurate modeling of skin-effect loss is so crucial.

Some of the assumptions made during SI analysis are easily overlooked. For instance, most SI models are supplied using the I/O buffer interface specification (IBIS) standard. IBIS buffer models specify best-case and worst-case switching behavior based on specific, predetermined combinations of process, temperature, and voltage. These mixtures are contained in the IBIS model file along with the buffer's behavioral data. If any of these operating conditions are exceeded, the results of any SI or crosstalk analysis using these models are invalid.

The buffer model specifies the worst-case and best-case supply voltages at the die. If the voltage at the die drops below the worst-case voltage listed in the IBIS model, the device will respond more slowly than the worst-case response predicted by the model. Therefore, SI and crosstalk analysis rely heavily on assumptions about the adequacy of the decoupling capacitors and their ability to regulate the power delivered to the chip.

The worst-case voltages in the IBIS file are determined by the semiconductor manufacturer. There are no established procedures for determining which worst-case voltages to use. IBIS models from different vendors may have different worst-case voltage values, even though the devices operate from the same supply voltage. When multiple sets of worst-case voltages are specified, the most conservative values should apply.

Another important, idealized as-sumption made by most SI tools is that the power and ground planes behave ideally at the point where the chip attaches to the board. In such cases, the planes are modeled assuming that they can deliver infinite power in zero time. While some SI tools have provisions for modeling power/ground noise, they fail to analyze nonideal power and ground plane behavior at the board level. Instead, they confine this modeling to the power-distribution system within the package itself.

As a result, modern digital designers must juggle the discontinuity between SI/crosstalk analysis and power-system design. They have to ensure that their pc-board decoupling strategy is adequate to maintain certain minimum voltages. This must be done despite the fact that they can't rely on the SI tools to help validate the performance of the decoupling structure.

In a perfect world, the power planes in a pc board would be able to source large amounts of current instantaneously. Ground planes would exhibit similar current-sinking characteristics. But in the real world, this isn't the case. Ground and power planes have finite, nonideal parasitic values. Any significant amount of current drawn through the plane will therefore have a voltage drop associated with it. This voltage differential will cause the chip's ground reference to be at a higher voltage than the power-supply ground. Large currents that flow through the parasitic inductances presented by the power plane will act in a similar fashion. These currents will cause the voltage at the chip power pins to be at a lower potential than at the supply output.

Demands for large currents could occur because the device outputs are changing state, as they usually are. In this case, the voltages at the chip power and ground pins will "jump" when the device changes state. They'll return to normal as the device output settles to its quiescent value. This phenomena is often referred to as ground/power bounce. It causes the most severe problems when multiple pins of the device switch in the same direction (all high or all low) at the same instant.

These are called simultaneous switching outputs (SSOs), and the associated voltage fluctuations are often called simultaneous switching noise (SSNs). SSO and SSN are often used interchangeably, although one refers to the noise produced while the other identifies the event that produces it. The switching noise in the die might exceed the worst-case voltage parameters specified by the SI model. If so, the results of the SI analysis are invalid and the system-analysis process falls apart.

As mentioned previously, we refer to the combination of the power supply, voltage-regulator modules (VRMs), bulk capacitors, high-speed decoupling capacitors, and the power planes as the power-distribution system. In modern designs, these PDS components interact with each other in the course of supplying power to the chips. Voltage-regulator modules (VRMs) provide locally controlled sources of voltage at specific locations on the pc board. These devices automatically regulate voltage based on demand for current. They have a finite (slow) response time, however. In fact, the VRM feedback loop is slow enough that the VRM typically can't respond to instantaneous surges in demand for current on the order of 100 µs or less. In such cases, the demand for current comes and goes, but the VRM simply never sees it. Therefore, the VRM cannot service instantaneous power requirements for those devices switching at frequencies higher than 10 to 100 kHz.

Electrolytic capacitors provide large reservoirs of charge. But the parasitic inductances associated with their leads and with the connections within the capacitors themselves limit the maximum frequency at which current can be delivered. In practice, electrolytic capacitors generally can't respond to demands for current much above 1 MHz.

Servicing switching events is therefore left up to high-frequency decoupling capacitors that are placed as close as possible to each high-speed component. These capacitors must be located close to devices being decoupled for two reasons:

  1. The parasitics between the capacitor and the switching device must be minimized. This is because the associated parasitics and resistances will limit the amount of high-frequency current that can be supplied to the device.
  2. Electrical wave fronts move at a finite rate. To sustain the device's switching speed, the current from the capacitor must be able to reach the switching device quickly, typically in less than one-fifth of the rise time.

The decoupling capacitor's parasitic values and the inductance formed due to the connections to the power and ground planes are critical parameters. They determine the frequencies at which a high-speed, decoupling capacitor will be effective.

The final components in the PDS are the power planes themselves. If properly designed, they can serve as reservoirs of distributed, high-frequency charge. The efficiency of the power planes for high-speed decoupling is highly dependent on the characteristics of the pc board's stackup. This refers to the conductive planes' closeness to each other, the thickness of the layers, the dielectric constant of the insulating layer, the shape and size of the planes, and the number of holes in the planes due to vias. In most modern designs, the power-plane layers don't provide significant decoupling capacitance below a few hundred megahertz. Above 350 MHz, however, the power planes provide the only significant decoupling at the pc-board level.

Ideal capacitors exist only as mathematical models. All real capacitors have parasitic inductances and resistances that occur in series with the device capacitance (Fig. 1). Because of these inductance and resistance values, the capacitor behaves as a series RLC circuit. At low frequencies, parasitic inductance has a negligible effect on circuit operation, and the device's capacitive reactance predominates. Conversely, at high frequencies, the parasitic inductance becomes dominant and the device exhibits expanding inductive reactance with increasing frequency.

The terms "low frequency" and "high frequency" are relative to the resonant frequency of a specific capacitor. At its resonant frequency, the effects of the capacitor's capacitive and parasitic inductive reactances cancel each other, leaving only the equivalent series resistance (ESR) of the device (Fig. 2). This is as good as it gets. The impedance of the capacitor never gets any lower than it does at this frequency. So, its ability to source or sink current is at its maximum.

At all other frequencies, the device exhibits frequency-dependent impedance (higher than ESR) that limits the amount of power the capacitor can deliver to the load in a finite amount of time. The fact that decoupling capacitors are maximally effective at their resonant frequencies and less effective at all other frequencies is a fundamental and critically important concept.

A pc board always contains a collection of different capacitor values with different resonant frequencies. For this reason, the board's ability to deliver power to the components at different frequencies will vary. Some frequencies will be better serviced than others.

We can determine the frequency requirements for the power-distribution system by examining the switching behavior of the components in the system. An ideal square wave can be represented by a sum of a series of sinewaves in a Fourier series:

V(t) = sin (ωt) − 1/3 sin(3ωt)
+ 1/5 sin (5ωt) − 1/7 sin(7ωt) + ...

Therefore, an ideal square wave consists of a sinewave at the fundamental frequency plus multiples of all the square wave's odd harmonics. Each successive harmonic is diminished in amplitude, as denoted in the equation. The square wave can be plotted by adding successively more of the harmonically related sinusoidal components. Once this is done, it's interesting to observe how the signal begins to more closely approximate the square wave itself, as more of the sinusoidal components are added (Fig. 3).

As shown, for a bus switching at 100 MHz, the magnitude of the sinusoidal components at 500 and 700 MHz are significant. Incidentally, the reason that very high frequency digital signals tend to look somewhat like sinewaves is that skin-effect loss causes escalating resistance with increasing frequency. So for very high frequency signals, the upper harmonics become attenuated to the point where they simply vanish.

When the maximum instantaneous (switching) current and the permissible power droop (supply ripple) are known, Ohm's law can be used to calculate the maximum allowable impedance of the power-distribution system. As an example, consider that IINST,MAX = 10 A and VRIPPLE,MAX = 100 mV. Then the maximum allowable impedance of the power-distribution system is R = E/I = 0.1/10 = 10 mΩ at all frequencies of interest. This means that the power-distribution system must provide the components with a very low impedance path to the power and ground supplies for the system to work properly.

This problem of providing very low impedance paths has become more severe with each succeeding generation of computer technology. As operating voltages continue to drop and currents increase, the allowable ripple on the supply planes also drops (see the table).

From the table, we could conclude that last year's challenge was to create a power-distribution system that maintained a 1.8-mΩ impedance out past 3 GHz! What design and analysis techniques could one possibly use to get a handle on this problem and solve it? (Fig. 4)

System Exhibits Distributed Behavior
Remember that the PDS consists of multiple components, each with its own unique impedance versus frequency response curve. The components are distributed around the pc board, so the PDS behaves as a distributed network. Different regions of the pc board will exhibit different impedance/frequency profiles. The design task then becomes to design, model, and verify a PDS that holds the maximum frequency-dependent impedance of the PDS below the target impedance level across all of the critical regions of the board.

While the ideal impedance versus frequency curve for the PSD would be flat, the real curve is far from it. If we could simply place all the different devices "on top" of each other at the same location on the pc board, the corresponding impedance characteristic would be the frequency-domain combination of the individual device curves.

The regions of maximum impedance occur between the resonant frequencies of one device class and another at what can be thought of as frequency transition regions between the different components. These regions are referred to as "antiresonances" and present significant problems that need to be addressed as part of any PDS design. The farther apart the resonant frequencies are spaced in frequency, the more pronounced the antiresonance peaks become (Fig. 5).

It should be clear that it's highly beneficial to use a large set of different capacitor values in the PDS. This is because of what happens when we combine capacitors of different types, each exhibiting different resonant frequencies. This has the effect of flattening out the PDS impedance curve and maintains its upper bound at a satisfactory value.

Practical experience has shown that the biggest problems with antiresonance take place at the high end of the frequency band. They occur beyond the point at which the decoupling capacitors' effectiveness falls off, but before the power-plane distributed capacitances become effective. Decoupling capacitors typically don't service demands beyond 100 MHz. Power planes, on the other hand, are seldom beneficial below 400 MHz. To fulfill the requirement for current in the 200 to 500 MHz range, we need to extend the serviceable frequencies associated with high-speed decoupling capacitors—or else redesign the power plane to be more efficient at lower frequencies. In either event, we also need the design process and analysis tools to enable us to predict the design's behavior as we make changes.

There are ways to make decoupling capacitors more effective at higher frequencies. First, we can use high-quality, low-ESR capacitors to minimize the impedance of the PDS. But low-ESR capacitors are a double-edged sword. Used properly, with minimal current-loop area, these devices can deliver suitable low impedances and reduce component count. If used improperly, however, these components create large, high-frequency currents that are virtually guaranteed to create radiation problems. Nonetheless, with careful attention to decoupling capacitor design, we can substantially narrow the gap between the effective frequencies of the decoupling capacitors and the power planes.

To maximize the efficiency of the high-frequency decoupling capacitors, we need to minimize both the loop area and loop inductance (Fig. 6). The fanout strategy used for the decoupling capacitors has a large impact upon these parasitics. Fortunately, we can use 3D field solvers to characterize loop inductance of different fanout strategies and determine the optimum physical design for device fanout.

The progress that has been achieved in optimizing fanout strategies over the years is shown in Figure 7. Capacitor fanout length has gradually decreased to the point where further reductions in loop area are driving the adoption of new manufacturing techniques such as via-in-pad design.

The key issue now is how to predict and optimize the design of power planes. Without a good design-and-analysis methodology, one of two outcomes may occur. Power planes may respond inadequately, thereby increasing common-mode EMI that can radiate from cables and possibly cause system failure. Or, the decoupling system may end up being over-designed,
driving up system cost unnecessarily.

Traditional SI simulation approaches have concentrated on modeling circuit behavior in the time domain. This is true of almost all current SI- and crosstalk-analysis tools. An SI analysis typically assumes that the behavior of the pc-board power and ground planes is ideal. To accurately predict the effect of the PDS response, the traditional circuit model must be augmented with a power-distribution model. The combined response of the device output and the PDS is then analyzed.

This is a good example of a "verification-based" approach. It emphasizes accuracy over speed, requiring a lengthy analysis to predict the detailed behavior of a single set of outputs. But this type of analysis is not conducive to the design process, where the designer wants to create an initial configuration, run a quick simulation, and then make adjustments to the design, based on the results of the analysis. What's more, lengthy, time-domain analysis can validate the behavior of only a single driver output, and there are thousands of them in an average pc board.

Another significant problem is that time-domain analysis assumes that the demand for instantaneous current is driven by the I/O ring, rather than by the device core. For devices that have a "standby" low-power mode and can "wake up" in a single cycle, this is a grossly optimistic assumption. The peak demand for power will occur during device wakeup, and time-domain analysis of output switching behavior simply won't predict this.

A new and different approach is to analyze the behavior of the PDS by itself in the frequency domain. If the maximum instantaneous current and permissible PDS voltage drop are known, then the maximum allowable PDS impedance can be determined simply from Ohm's law. For all frequencies with significant currents, the PDS must present an impedance equal to or less than the target impedance. The goal is still to design a PDS that "meets or beats" the target impedance at all points on the pc board. But the analysis strategy changes considerably.

The power and ground planes can be represented as a distributed electrical circuit. This can be illustrated as a matrix of R, L, G, and C values, or better yet by a transmission-line mesh. The pow-er/ground planes are meshed and converted into a network of nodes that represent the distributed behavior of the planes. Bulk and decoupling capacitors are represented by their bulk capacitance as well as their parasitic inductive and resistive values. They're then connected to the appropriate nodes in the mesh. Voltage and noise sources can be connected to the mesh to model the behavior of supplies and the devices, creating demands for instantaneous current.

Once the PDS model is created, it can be analyzed in the frequency domain, thereby determining the impedance of each node over the frequency range of interest. The transimpedance value for each node in the mesh represents the frequency-dependent PDS impedance that a device would see if its power pin were attached to the power or ground plane at that point. This can be analyzed and plotted to determine if the PDS meets the target requirements. Any problem areas in the design can be identified and the design can be changed, repeating the process until satisfactory performance is achieved. This methodology critically depends on several factors:

  • Accurate modeling of capacitor parasitics. Values are obtained from precision measurements. Fortunately, practical experience has demonstrated that parasitics can be estimated if the capacitor material technology and dimensions are known.
  • Accurate modeling of decoupling-capacitor loop inductance. Loop inductance is a primary factor in determining the upper frequency limit of a capacitor's effectiveness. 3D field solvers are used to model the device's connection to the power planes and determine the loop inductance.
  • Accurate modeling of the power plane parasitic values. This also is well suited to 2D and 3D field solutions.
  • Fast and accurate frequency-domain analysis of the combined structure.

The design process just described can be performed using a standard netlist-driven analysis approach. But the task of changing the values and location of capacitors would become incredibly difficult. The job of correlating the simulation results versus the regions in the pc-board layout would become tougher as well.

Therefore, integration with a graphical pc-board design tool is preferable. This way the user can place devices graphically in the pc-board layout and then quickly correlate simulation results with regions of the pc board for debugging. Integration with the pc-board design tool simplifies the design process, speeds iterations, and greatly reduces the overall chance of error.

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