Electronic Design

PC-Board Design Tools Step Up To Gigabit Challenges

Fast edge rates and signal-integrity issues are hitting pc-board designers harder than ever before, calling for design tools with enhanced analysis capabilities.

Depending on the type of product you're involved with, pc boards represent a range of design challenges. Generally speaking, you'd like to produce your board for as little money as possible, making sure that it's testable and manufacturable without hitches. It would also serve you well to look beyond the board itself at how it meshes mechanically with the rest of the system it's destined to be part of.

Yet in addition to those general engineering concerns, if you're looking at a board carrying extremely high-speed signals, board design presents some signal-integrity issues that could keep you awake at night.

One thing is certain: Boards are now more densely packed than ever. What constitutes the upper echelons of today's pc-board design work? The inner layers are being designed with trace widths of 4 mils and edge-to-edge spacing of 4 mils. On the outer layers, spacings are 5 mils (trace widths) and 5 mils (edge-to-edge spacing). These closely spaced traces open designers up to serious signal-integrity problems, with great potential for capacitive coupling and crosstalk between signals.

Not only are traces close together in the X axis, they're tight in the Z axis, too. The number of layers on boards varies with industry and application, but it's safe to put it in the range of 12 to 24 layers. You'll see as many as 50 in extreme cases, but that's the "lunatic fringe."

Then there are the devices with which boards are populated. Currently, ball-grid array packages sport 0.8-mm lead pitches with 1500 to 2000 I/Os. Pitches are getting tighter, though, with 0.5 mm on the way. That will translate into I/O counts of around 3000, leading board designers to perform even more fancy footwork to accommodate them while preserving signal integrity.

Along with spiraling density come increasing signal speeds and clock rates. On-board memory buses are running in the 500-MHz range with 1 GHz not too far off. In communications, the OC-48 communication protocol calls for data rates of 2.5 Gbits/s. That rate is heading toward 10 to 40 Gbits/s.

The result is digital signals that don't look like digital signals anymore. Multi-gigabit signals bring rise times of less than 100 ps. For a 10-Gbit/s signal, you could be looking at 25 ps. "A square wave is never perfectly square in practice," says Bill Wignall, president of Electronics Workbench. "There's overshoot, undershoot, ramp time, and ringing. Those effects are much more problematic if the speed at which the circuit needs to settle, or the time after which it's supposed to have reached its steady state, is shorter and shorter."

Thus, signal-integrity analysis be-comes a critical element in high-end pc-board design work. But it's not the only critical aspect. The tools must address other elements of the process well, even for boards that don't necessarily represent the cutting edge of design in 2002.

At the very outset of a board design, be mindful of partitioning. "Board design is not just a matter of buying components and sticking them onto the pc board and routing it," says Phil Loughhead, Protel product manager at Altium Ltd. "It's about designing a system or product, and there are a variety of ways you might choose to implement that product."

A particularly important element of the flexibility that designers must have in terms of partitioning and its impact on board design is the growing use of FPGAs. "The team doing the huge FPGA design is probably a completely different team than the one doing the high-density pc board," says Andy Watts, product marketing manager for solutions marketing at Mentor Graphics. "Traditionally, they have had different tool sets. All the timing constraints that affect the data, on and off that chip, have to be passed into the other flow."

Changes made in the FPGA's pinouts must be reflected in the board layout. Mentor's tools, for example, can take the pinout change data from the FPGA onto the board in a one-step process as opposed to doing it manually.

Altium's Protel DXP full-board-level design environment also supports FPGAs. The tool features macro libraries for Altera and Xilinx devices, which let designers work in the schematic paradigm inside the FPGA, and takes them straight to a place-and-route tool. Like the Mentor tools, it facilitates early partitioning of designs between programmable logic and other functionality on-board (Fig. 1).

Another area that should be of concern to pc-board designers is simulation. One might think all pc-board designers consider simulation to be an important part of their flow, but that's not true. Often, designers are intimidated by the prospect of simulation, says Electronic Workbench's Wignall.

What's so intimidating about simulation? Some designers have difficulty using pc-board simulation. "Many simulators, over the years, presented the simulation to the user in a raw form. So the user had to see the simulation language at work. They didn't want to learn the intricacies of IBIS (Input/Output Buffer Information Specification) or Spice models," says Wignall. Today's pc-board tools have eliminated this difficulty, making simulation a pushbutton matter. An example is Electronic Workbench's Multisim tool, which allows users to run Spice simulations directly from their schematics (Fig. 2).

The other problematic part of simulation is the perception that users could not adequately simulate all of the devices on their board due to the models' complexity. Also, some users were put off by the fact that while simpler components could easily be modeled in Spice, the method of choice for board-level simulation, others could not.

The advent of simulators that handle mixed levels of abstraction in the pc-board realm has removed this hurdle from the simulation path as well. Multisim permits mixed-mode simulation of Spice along with VHDL or Verilog representations of devices that are simply too complex to be modeled in Spice.

The signal-integrity issue for high-speed designs begs some questions as to the designer's abilities. For one thing, many digital designers get in way over their heads in trying to resolve signal-integrity problems in board designs. "A lot of computer engineers don't take transmission line courses," says Rob Hinz, principal engineer at SiQual, a consulting firm that specializes in interconnect engineering. "They treat wires on pc boards as idealized connections."

Hinz points out that in a high-speed situation, every aspect of the interconnect needs to be meticulously and deliberately designed to preserve signal integrity. "That means the engineer has to look at how his pc boards are manufactured. What's the layer stackup? What are the materials involved? What choices are being made to control impedances? What are the manufacturing variances that you have to account for?"

All of these factors translate into electrical constraints on the design. "Today, it's not uncommon for 50% of your board to be constrained," says Jaime Metcalfe, vice president of strategic marketing for Cadence's pc-board systems division. "Some boards can be 90% to 95% constrained." When your nets are constrained, that adds an extra level of complexity to the way you design the board. It's not a connect-the-dots problem anymore.

It's important that pc-board tools used for high-end designs allow engineers to define constraints as early in the process as possible. Having access to timing analysis tools and the ability to apply timing constraints directly to the design is critical.

Here's where virtual prototyping of pc-board designs is a key step in the process. Tools must let designers start from a schematic, explore different driver-receiver technologies in given nets, and do what-if analyses with various board stackups. One tool that meets this description is Zuken's Hot Stage, a prototyping tool that provides constraint management in a spreadsheet view of all the networks in the design.

"Designers can specify the length and other attributes, impedance properties, and feed them to an automatic router," notes Michael Dzado, CAE applications engineer at Zuken. "Users can specify critical nets so they can be routed and placed first. Then they can constrain the router such that when a design person lays it out, he can get visual indication of whether he's met the constraints for this specific network or not." After routing, Hot Stage performs post-layout simulation to determine whether or not the constraints captured from the schematic were met.

Routing of pc boards is another key area that has lately seen some innovation. Routers must handle more than blind and buried vias these days. We're now in an age of high-density interconnects (HDIs) on pc boards, replete with exotic microvias. The signal-integrity implications here give most pc-board designers a hard time (Fig. 3).

The pc-board world has taken technology from the silicon world in terms of deposition approaches for interconnect as well as for dielectrics used in microvia buildup technologies. Mi-crovia constraints and structures are even different from traditional pc-board blind buried vias. "This has been a hiccup for a lot of routers in the industry," says David Wiens, market development manager at Mentor Graphics. "We had to update our technology to support it."

Notable among current autorouters is the one within Altium's Protel DXP board-level design package. The Situs autorouter employs a topological analysis technique to map the board space. Unlike grid- or shape-based routers, which are geometrically constrained in terms of the possible route paths they can identify, the Situs autorouter builds a map using only the relative positions of the obstacles in the space without reference to their coordinates. As a result, the router isn't limited to purely vertical or horizontal paths.

From a signal-integrity standpoint, it's interesting to consider that pc-board designers have long been dealing with issues that have just recently hit IC designers. Due to the relatively larger geometries of structures on boards, board designers have struggled with inductance and crosstalk for some time.

From the beginning stages of a board design, there are methods that designers can use to avoid signal-integrity problems downstream, especially if cost considerations dictate the use of tried-and-true FR-4 in high-end applications (see "Wringing More Performance From FR-4," p. 70). Careful floorplanning is one of them. Problems in this area can stem from having different people perform schematic capture and layout.

"Simulation and floorplanning is much more logically done by the person who does schematic capture than by the person who does layout," says Electronic Workbench's Wignall. "Often, that's the same person. But if not, it's the guy who enters the schematic who has a general idea about how the circuit functions electrically, whereas the pc-board designer is the guy who figures out whether to place an IC in the top left corner or the bottom right corner. He makes sure everything's there and connected and manufacturable but often does not understand how the circuit operates."

Ultimately, though, for a high-speed board, signal-integrity analysis comes into play. According to Cadence's Metcalfe, "Because of the geometries and frequencies we see on a pc board, we're moving more and more toward solving the complete Maxwell equations. And we're able to make fewer and fewer assumptions to simplify the problems."

It's no longer possible to analyze signal integrity solely in terms of board traces at gigahertz speeds. "Designers must look at the timing from die to die instead of from pin to pin," says Metcalfe. In the past, designers would have some timing budget for the interconnect from the pin to the die and treat that as part of the overall timing. But it would be a relatively unknown quantity compared to the board traces. Now, the approximations used to guesstimate what happens between the die and the board are falling apart.

On the board itself, signal speeds cause assumptions and approximations to fail, too. For instance, what happens to signal integrity when traces carrying a differential pair turns a corner? Designers must concern themselves with intra-pair signal skew for differential signals, and skew with respect to the clock for single-ended signals.

Structures like trace bends, microvias, and others complicate signal-integrity analysis because they're difficult to model accurately. Consultants like SiQual's Hinz rely on full-wave 3D field solvers for such tasks. Tools, including Ansoft's Spicelink with both 2D and 3D field solvers and a Spice simulator, fill the bill for such applications (Fig. 4). Spicelink, now available in Version 5.0, produces accurate 3D distributed models. It also includes an IBIS driver to run system simulations.

When designing transmission lines, for instance, impedances must be controlled to prevent mismatches and reflections. Otherwise, you end up with intersymbol interference and other effects that cause errors in digital links. "Typically, you'd use a 2D solver because you just want to design the cross section of your transmission line," says Hinz.

That's fine for a straight trace because a 2D solver accomplishes a cross-sectional analysis of the trace at one point and treats it as a lumped element and outputs it as an RLC model. "You could characterize a 3D structure like a via with a lumped-element 2D solver," says Jonathan Smith, product marketing manager at Ansoft. At relatively low speeds, that RLC output would be acceptable to an experienced designer who is comfortable with analog effects.

But at high speeds, or in cases of nonuniform traces, 3D structures need to be characterized more accurately with distributed models. That's when a 3D solver is used to output a model as a distributed RLC network. "At that point, you lose the ability to just eyeball it and say the capacitance is too high or the mutual inductance is too high," says Smith. Looking at the waveform requires signal-integrity tools.

3D solvers also are required when ground planes aren't ideal. For instance, if the ground plane has cutouts or other irregularities, a 2D solver will be unable to characterize traces that encounter those nonuniform areas of the board.

Heavy-duty signal-integrity analysis tools, especially those involving 3D field solvers, aren't for everybody or every board design, though. All board designers should have an environment that produces pc boards with adequate functionality, on schedule, within budget, and in a fashion that's manufacturable. To that last point, relatively affordable design environments are available that go beyond board layout to show how the finished board will interface mechanically with the system.

One example, Electronic Workbench's Ultiboard layout software, includes a mechanical CAD module. This utility lets users draw accurate front panels, enclosures, and other mechanical pieces, ensuring that their board will mesh smoothly with the packaging it will ultimately reside in.

Need More Information?
Altium Ltd.
+61 2 9975 7710

Ansoft Corp.
(412) 261-3200

Cadence Design Systems
(408) 943-1234

Electronics Workbench
(800) 263-5552

Mentor Graphics Corp.
(503) 685-7000

SiQual Inc.
(503) 885-1231

Zuken USA Inc.
(978) 692-4900

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