As system-on-a-chip block sizes stretch to well over 1 million gates, chips must be divided into so many blocks, assembly can become impractical. But by integrating silicon virtual prototyping and second-generation global physical synthesis in one environment, Cadence has crafted a second-generation physical-synthesis tool. Its First Encounter Global Physical Synthesis (GPS) lets designers create much larger chips than was practical in the past.
Unlike first-generation physical-synthesis approaches that optimize a single logic path at a time, global physical synthesis optimizes timing for many paths concurrently. This dramatically reduces the compute effort needed for design convergence, even for very large blocks in short design schedules (see the figure). First Encounter GPS supports both RTL-to-placed gates and netlist-to-placed gates design styles.
In related news, Cadence and TSMC have jointly announced TSMC's Reference Flow 5.0. An integration of the Encounter platform with Cadence's Allegro system-interconnect design platform results in a flow targeting TSMC's 90-nm process technology. Techniques such as low-power synthesis, multiple supply voltages and power domains, leakage power optimization, automatic power-grid generation, and IR-drop analysis are all brought to bear.
With IC packaging a critical issue in nanometer design, the Allegro Package Designer is included in the TSMC flow to handle chip I/O and flip-chip issues. The tool spans interconnect-design domains from IC to package to board. It also supports feasibility analysis and design of the IC's bump array or die pads in the context of the package interconnect.
First Encounter GPS is available now starting at $375,000 per year.
Cadence Design Systems