Xilinx is a top supplier of field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). Customers can program these ICs in a laboratory to perform specific complex functions, achieving greater design flexibility while cutting time-to-market.
These logic devices are used to direct signal traffic within a digital system. The company also offers a broad range of design software and intellectual property used to customize its chips. Equipment manufacturers across a wide range of industries employ PLDs in their devices.
In addition to other sales channels and distributors, Avnet distributes the majority of Xilinx’s product line worldwide. Xilinx, which is “fabless,” buys most of its wafers from United Microelectronics. It also buys wafers from Seiko Epson and Toshiba. About 60% of sales are from overseas markets. And, Xilinx and its competitor Altera have cornered about 80% of the programmable chip market.
Despite the demand for these chips, Xilinx’s operating profit growth and margin improvement declined in 2007, along with its bonus points based on Electronic Design’s annual Reader Survey. Yet significant improvements in the company’s R&D expense changes and debt to equity ratio enabled it to relatively maintain its position, moving from 2006’s ranking at 73 to 2007’s tally at 72. And, bigger changes may lie ahead.
Moore’s Law is still alive and well in the PLD segment as costs keep being driven down. As a result, PLDs can be used in more consumer segments like flat-panel televisions, cell phones, and set-top boxes. More and more PLDs are also being used in the automotive segment as the cost of programmability drops.
In the past, customers got a chip and a compiler and then did everything themselves. Now, customers expect more IP cores, and Xilinx has a strong organization that develops and integrates IP cores for customers
In January, Wim Roelandts became chairman of the board, stepping up from president and CEO, where he served since 1996. Sales rose from $560 million to almost $2 billion in 2007 during his tenure. Moise Gavrielov is Xilinx’s new CEO and president. He is the former CEO of Verisity Ltd., an Israeli company acquired by Cadence in 2005. Gavrielov hopes to increase the sales base to $10 billion during his tenure. His strategy is to provide more complete solutions in terms of software, IP cores, and so on.
Application-specific standard product (ASSP) vendors provide a chip and software so the customer can just put it on a board and it works. For FPGAs to compete in and capture this segment, an integrated solution including the soft IP core along with the FPGA will have to be provided, as these soft IP cores work much faster than the hard IP cores in ASSPs. While an application-specific integrated circuit (ASIC) is designed for a specific application for one company, an ASSP is application-specific for more than one company.
Xilinx’s biggest opportunity lies in getting its PLDs used in high-volume markets. A decade ago, 60k units/year was big volume. Currently, the company’s biggest volume is 8 million units/year for a single socket, which is used for a flat-screen TV system. The future holds even higher volumes in high-end products. Eventually, those volumes will be seen in lower-end products.
Another opportunity is to provide more of an integrated solution. Today’s FPGA is really a hybrid between an ASIC and an FPGA, not just programmable logic. It has processors, transceivers, and many other components. Adding a few hard IP cores to the chip significantly increases the value provided without increasing the size by much. Adding memories and digital signal processor (DSP) IP cores on chips adds value. Xilinx is adding more and more hard IP cores to its FPGAs, as performance and speed are improved and power consumption is reduced.
IP cores are blocks of digital logic designed to be implemented in an ASIC or FPGA chip. They fall into one of three categories: hard cores, firm cores, or soft cores. Hard cores are physical manifestations of the IP design. They’re best for plug-and-play applications and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard) cores also carry placement data but are configurable to various applications. The most flexible of the three, soft cores exist either as a netlist (a list of the logic gates and associated interconnections making up an integrated circuit) or as hardware description language (HDL) code.
The company appears to be in a strong position considering that it has little competition on the high end of its 65-nm design products. While its competitor Altera will move to 40-nm design in 2008, Xilinx is designing products at 40 nm as well. A new generation of products comes out every two years, and 65-nm products came out in 2006.
However, the trend toward more low-cost FPGAs could cause some cannibalization of the market. Although Xilinx feels that the never-ending battle to lower prices while developing new applications will continue, the company feels it has an advantage as it can capture new markets that would not have been possible without lower industry prices, so the increase in volumes would be a positive.
As for ASSPs being a threat to FPGAs, Xilinx feels ASSPs are the ultimate ASIC chip. Xilinx also believes fewer ASIC chips are being designed because of higher costs. ASICs can be replaced by an ASSP or a PLD. ASSPs have been very successful, but they ultimately have the same drawback as ASICs—they still only go to a few more customers, and they could also become economically unjustifiable. ASSPs will have to focus on the higher-volume sockets, and Xilinx feels PLDs will dominate lower-volume sockets due to lower costs.