The SP5730 phase-locked loop (PLL) frequency synthesizer can improve phase noise performance of digital television receivers by 10 dB compared with other solutions, it is claimed. The device can achieve this performance improvement with a wide range of division ratios, while reducing power consumption for digital terrestrial television (DTT) systems. Designed for tuning systems up to 1.3 GHz as required by the DTT standards, this device has ultra-low phase noise performance of 83 dBc/Hz within the loop bandwidth at a comparison frequency of 166 kHz and a LO frequency of 1 GHz. At comparison frequencies up to 4 MHz, high phase noise performance can be achieved to enhance receiver performance in developing service areas where adjacent channel and/or co-channel interference typically limits operation. Overall, phase noise performance is at least 6 dB better than other bipolar or BiCMOS devices at low comparison frequencies and greater than 10 dB at higher comparison frequencies, it's claimed. An evaluation board is also available upon request.
