Demands for low-voltage, high-current supplies in ever smaller form factors continue to fan the flames of innovation in power MOSFET technology. Recent progress made by semiconductor manufacturers in reducing the on-resistance and gate charge of their silicon has enabled steady gains in dc-dc converter efficiencies. However, the meteoric rise in silicon efficiencies over the last two to three years has seen the parasitics of the MOSFET package account for a sizable portion of the device's on-resistance. With that in mind, semiconductor vendors have begun crafting new package designs including ones that co-package multiple dies.
While packaging innovation continues, other silicon-design concerns such as the effect of the MOSFET's body diode on efficiency are also getting special attention. In addition, the relationship between MOSFET and gate driver is being scrutinized. For many transistors now in development, improved performance of the FETs will result from balancing several of its specifications to suit the application.
TOP TEN >ADVANCES IN TRENCH PROCESSES have pushed RDS(on) to new single-digit milliohm lows for low-voltage MOSFET silicon. At the same time, reductions in overall gate charge have produced parts with tens of nanocoulombs. In terms of silicon alone, MOSFET dies now exhibit figures-of-merit (FOM, which equals RDS(on) times QSWITCH) in the 40 to 60 range for industry-best devices. However, new devices will bring FOMs in the mid-20s. Another metric, RDS(on) times die size, is in the 20 to 30-mΩ × mm2 range. In the year ahead, expect further incremental reductions in these numbers. For example, a new generation of devices from International Rectifier is expected to expected to achieve RDS(on) × die size ratings below 15 mΩ × mm2.>FOM RATINGS FOR PACKAGED MOSFETs are sinking below 100. For example, there are currently D2PAK-style 25-V devices with 5 mΩ or less of RDS(on) and gate charge around 20 nC. However, with board space at a premium, the need for better performance in the smaller, SO-8 format has led semiconductor vendors to develop a number of new SO-8-compatible replacements with reduced values of RDS(on), inductance, and thermal resistance. Unfortunately, each vendor has a different approach to package design, and customers have been left with many choices, but little in the way of standardization. Expect this situation to persist until customers and vendors get behind one or more packaging options.
>CO-PACKAGING OF MOS-FETs and gate drivers within multichip modules (MCMs) should become more popular. This co-housing of dies reduces the effects of pc-board layout on the performance of these parts in dc-dc converters. Expect new packaging approaches to emerge.
>HIGH-VOLTAGE MOSFETs aimed at offline switching applications will also achieve better FOMs. For example, Infineon's CoolMOS series of 600-V devices achieves 190 mΩ of RDS(on) in a TO-220 with overall gate charge of 103 nC. Continued development of such devices is expected to lower gate charge further.
>STACKING OF POWER SEMICONDUCTOR DIES is one new co-packaging approach being explored. Although die stacking, which shortens interconnect paths, has been popular for co-packaging logic and memory chips, this approach has not generally been applied to power semiconductors. That may be changing. Infineon recently unveiled an integrated switch (TDA21201) that co-packages an n-channel MOSFET, p-channel MOSFET, and gate driver in a TO-220. The two MOSFETs are placed side by side, while the gate driver is stacked on top of the n-channel device. The company applies a proprietary technique for handling the heat generated by the n-channel device as it affects the gate driver.
>IN ADDITION TO IMPROVING MOSFET silicon and packaging for lower figure-of-merit, device developers are looking at the reverse recovery characteristics of the body diode and then optimizing this element to improve overall power conversion efficiency. One vendor, Fairchild Semiconductor, is optimizing the reverse recovery of the low-side FET to make FETs that can work with a variety of gate drivers. Gate driver characteristics will be accommodated by tailoring the body diode.
>POWER-FACTOR-CORRECTION (PFC) boost circuits will continue to benefit from using silicon carbide Schottky rectifiers as replacements for standard high-voltage PIN diodes. The SiC diodes exhibit a reverse recovery charge an order of magnitude better than PIN diodes. As a result, diode losses can either be reduced or switching frequencies can be increased to reduce the size of the passive parts.
>WHILE DIE CO-PACKING CONTINUES, integration of power semiconductor functions (like the MOSFET and the Schottky) in silicon will also persist. Likewise, companies continue to integrate MOSFETs with controllers to achieve highly integrated dc-dc converter ICs with high-current outputs.
>IMPROVEMENTS IN HIGH-VOLTAGE semiconductor processes will push voltage limits beyond 60 V, making it possible to build more highly integrated pulse-width modulation (PWM) controllers. National Semiconductor will use a 100-V analog bipolar-CMOS-DMOS process to integrate a startup regulator with the PWM controller. This allows the controller to operate directly off of a 36- to 72-V input.
>CAR MAKERS will benefit from power conversion devices that boost alternator output. Recently, International Rectifier (IR) developed a module for implementing active rectification of the alternator output. Compared to conventional diode-based rectification, the FET-style bridge circuit in IR's Active Integrated Rectifier Regulator boosts the power available from a standard alternator by as much as 25% at idle speed.