Electronic Design

Power-Supply Design Issues

If the Core Duo is any indication, there's no slackening in what amounts to the power corollary of Moore's Law. Chips not only get denser and faster over time, despite the shrinking operating voltages that come with smaller process geometries, their peak power demands also continue to climb.

Gene Sheridan, vice president of International Rectifier's computing and communication business unit, says that future mobile processors and chip sets will demand 30 to 50 A of peak current. The CPU alone will need 40 to 70 W of peak power.

Even assuming there are still untapped ways to improve overall efficiency that can restrain, or actually shrink, overall power consumption, tomorrow's ac-dc supplies will need to deliver more energy when called upon. Sheridan figured on values as high as 150 W. That's good news for IR, because the company is well positioned not only with respect to low-loss switching FETs, but also in terms of power-factor-control ICs.

One looming question concerns the present power distribution topology, which provides dc at the 19- to 24-V level that is then bussed around the board. This is finally stepped down at the point of load (POL) by voltage regulator modules (VRMs).

Most of the power people I've asked think this approach still has a ways to go. But one maverick, Vicor's Patrizio Vinciarelli, has toured the globe pushing a radically different topology. In fact, Vicor proposes two options. Both are based on the latest addition to the company's Factorized Power architecture, which it calls a power factor module (PFM).

The PFM's step-down module automatically configures its step-down ratio based on the ac input voltage—90 to 132 V in North America or Japan, or 180 to 264 V in the rest of the world. The reduced voltage is applied to an isolated buck-boost module in the same package that also supplies power-factor correction. For the sake of simplicity, let's just say that these modules are much more sophisticated than conventional bricks and non-isolated POLs, and their switchers operate at higher frequencies.

In one of Vicor's proposals, a single PFM replaces the conventional ac-dc adapter's boost converter and down-converter. In a normal (for today) power situation, this increases power density by a factor of about five while reducing wasted power by around 4.5 W.

A more aggressive approach would be to maintain the adaptive step-down module as the only element in the external ac adapter, while the rest of the circuitry along with energy storage and a battery charger is moved inside the laptop. This significantly shrinks the external adapter's size, boosts power density by a factor of 10, and cuts external power losses to about 3.8 W.

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