Processors Automatically Shut Down To Save Power

The multicore Opteron processors in AMD’s “Shanghai” line are designed for performance, but their new Smart Fetch technology can also save power. A core can detect when a thread becomes idle. After a programmable delay, the core flushes its L1 and L2 cache to the chip’s L3 cache before shutting down. In addition to a faster startup, this gives other cores access to the core’s working set. Power savings up to 21% are possible when cores aren’t running full-tilt.

The chip’s 8-Mbyte L3 cache makes it easy to flush the L1 and L2 caches. The new cache is four times larger than its predecessor, leading to a typical 40% increase in Java and database application performance. Part of this increase is also due to the chip’s ability to perform a “world switch” faster, which is critical to virtual machine (VM) environments. Enhanced rapid virtualization indexing (RVI) support handles the world switch.

A new memory controller architecture improves performance using existing, low-cost DDR2-800 memory. This includes cache probe latency that has been cut in half to three cycles per operation. Cache coherency can now be checked during prefetch, providing higher throughput. Also, the chips are pin-compatible with existing Opteron processors and motherboards that use the F1 socket.

Each chip employs three HyperTransport 3.0 interfaces delivering bandwidth up to 17.6 Gbytes/s. AMD also is using immersion lithography to build the new 45-nm based chips. This technology will be required for the next generation of 32-nm silicon. It adds a layer of pure water between the lens and wafer to improve optical resolution.

The initial crop (2.3 to 2.7GHz) of 75-W chips is in the channel already. Existing motherboards can handle the new chips with a BIOS upgrade. Next year, AMD will reveal its 65-W and 105-W versions, expanding power and performance in both directions.

Live migration of VMs is now common in homogeneous environments that contain the same type of processor chips. It allows active VMs to be moved from one system in a cluster to another. This feature requires hardware support, but it can be found in chips like AMD’s Shanghai Opteron and Intel’s Dunnington Xeon.

Intel’s and AMD’s latest chips are designed to support migration across their lines of chips, enabling new platforms to be incorporated into existing clusters. Recently, Red Hat tried this trick with an AMD and Intel server. In theory, this will allow mixed-cluster environments to provide live migration support across the cluster.

One challenge lies in dealing with the instruction differences between Intel and AMD chips. Compilers can already generate applications that use a subset that will run on both platforms.

BILL WONG

See associated figure