Electronic Design

Rambus And SPMT Offer A Memory Of Things To Come

Memory is more than double data rate (DDR), as any embedded designer will attest. Memory technology is also one of the arenas where there is an ongoing conflict between standards and innovation. Volume keeps memory costs down, but it also means standards need to exist so parts are interchangeable.

Plenty of memory technologies are out now, with more on the drawing board. Two new possibilities, multithreaded DDR RAM from Rambus and serial port memory from the Serial Port Memory Technology Consortium, look to provide higher throughput with lower power requirements and more capacity in a compact package, even though they target different application areas.

Rambus has designed multithreaded RAM to deliver more performance for single-ended signalling technology used by the latest DDR3 memory (Fig. 1). Changes in the processor interface are required before designers can take advantage of this type of memory, but it can coexist with existing DDR3 memory implementations. It targets multicore processors.

Multithreaded RAM looks to reduce power consumption by 20% while running in threaded mode compared to the conventional non-threaded mode. It reduces the number of transactions by a factor of two and doubles the size of the transactions.

This approach uses the same memory chips as a conventional DDR3 dual-inline memory module (DIMM). Operating systems already need to account for multiple banks and controllers. This simply extends the process inside the DIMM.

Rambus is working with a major memory provider, Kingston Technology, to deliver multithreaded memory so it will be available if processor designers take advantage of the architecture. Multithreaded memory can plug into a conventional system and operate in non-threaded mode. Likewise, non-threaded memory can plug into a threaded system. It is all in how the memory and memory controllers are set up when the system boots.

The Serial Port Memory Technology (SPMT) architecture from the Serial Port Memory Technology Consortium is designed to use high-speed serial links that operate in an asynchronous, transaction fashion similar to PCI Express (Fig. 2). But the similarity ends there.

SPMT uses a low-overhead transaction system since it does not require features found in other systems such as complex routing. Likewise, the short connection distances result in a low bit error rate (BER) that eliminates the need for more complex error correcting mechanisms and increases available bandwidth.

A wide range of bit rates is defined for maximum power management and minimum radio interference. The bit rates also are defined to handle different host requirements and capabilities. The top end defined so far delivers 12 Gbytes/s with eight ports.

Multiple ports can deliver data to different processors in a multicore device often found in mobile devices, simplifying host design. SPMT uses the same protocols as parallel memory offerings with a 60% to 80% pin savings. Energy savings could be up to 50%.

These are just a few hints of things to come in memory technology.




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