Raytheon developed its MONARCH (Morphable Networked MicroArchitecture) architecture and chip under a Defense Advanced Research Project Agency (DARPA) polymorphous computing architecture contract from the U.S. Air Force Research Laboratory (see the figure).
It is designed to outperform existing quad-core processors by a factor of 10 in environments that MONARCH was specifically designed for—in this case, processing large amounts of sensor data for applications such as video and radar analysis.
The chip's field-programmable computer array (FPCA) operates in one of three modes: MIMD, SIMD, and Stream. The various hardware clusters are configured to support the current operating mode. A high-speed ring delivers data between compute, storage, and interfaces at 43 Mbytes/s.
The MIMD configuration lets independent applications run on the RISC processors. The SIMD operates the processors in an Altivec-like vector mode. These modes typically are programmed using C. The Stream architecture takes advantage of the crossbar fabric in the FPCA but tends to be more difficult to program.
Multiple chips can be linked together using the differential inter-FPCA links (DIFLs). Four chips can easily fit onto a single VME board. Serial RapidIO provides access to off-chip peripherals and services. The platform suits rugged and space environments.
FPCA Modes Of Operation