The RAVE verification system is expected to play a critical role in mainstream system-on-chip (SOC) design. The reconfigurable prototyping system takes advantage of two recent technological advances: the development of very large FPGAs and bonded-out cores that support any natural virtual component/block partition; and the evolution of SOC designs to modular bus-based and platform-based architectures. This evolution simplifies the complexity and increases the performance of interconnection modeling and functional integration.The RAVE system streamlines functional integration of SOCs. Users insert a small pc board, called a CoreBoard, into one of 31 available backplane slots. These CoreBoards contain an IP model in the form of an FPGA or a bonded-out core. Once in the system, interconnections between CoreBoards are routed automatically in the backplane to configure them as a virtual prototype of the target.