Electronic Design

SERDES With Adaptive DSP Brings 6.25 GHz To PC-Board Backplanes

More speed and longer product life—that's what equipment vendors look for when upgrading switch and router products, optical cross connects, Fibre Channel storage-area network and network-attached storage systems, and high-end servers. Accelerating existing FR-4 pc-board backplanes with new and faster serializer/deserializers (SERDES), or even copper cable interconnects, is one way to achieve that goal.

The D-PHY 5G family of SERDES chips from Analogix Semiconductor simplifies that task. These chips provide serial data speeds up to 6.25 Gbits/s over a maximum of 60 in. of FR-4 printed-circuit backplane. While current chips offer up to 3.125 Gbits/s, the D-PHY-5Gs extend this by using the usual programmable pre-emphasis and equalization as well as sophisticated DSP-based processing like adaptive equalization, adaptive crosstalk cancellation, adaptive echo cancellation, and error-correction coding.

Known as WideEye technology, this collection of DSP methods provides improved performance over existing backplanes. Unlike some SERDES that use multilevel pulse-amplitude modulation to achieve higher speeds, this product takes advantage of conventional NRZ binary coding. It also complies with the Optical Internetworking Forum's Common Electrical I/O (OIF CEI) 6G+ standard.

The D-PHY 5G series comes in two versions. The 4x5G with four high-speed links provides up to 25-Gbit/s full-duplex operation. The 2x5G version with dual transceivers performs up to 12.5 Gbits/s. Each device possesses eight low-speed 800-Mbit/s to 3.125-Gbit/s SERDES links. These XAUI-compliant CML I/Os are multiplexed into one 3.2- to 6.25-Gbit/s serial stream for backplane transmission. Three multiplexing options—1:1, 2:1, and 4:1—simplify interfacing with ASICs and FPGAs.

Integrated are built-in self-test (BIST) functionality and a comprehensive set of diagnostics and test modes for both low- and high-speed loopback evaluation using built-in PRBS generators and error checkers. The chips also provide for bit-error rate (BER) monitoring by polling MDIO or I2C controlled WideEye DSP registers. The MDIO registers can also control the various DSP functions, letting designers turn off selected parts of the chip to reduce power.

The D-PHY 5G transceivers consist of 0.13-µm CMOS and come in a 19- by 19-mm, 260-pin Heat Slug ball-grid-array (HSBGA) package. Pricing for the 4x5G and 2x5G units is $49 and $28 in high volume, respectively. Samples are available now, with volume production scheduled for after June.

Analogix Semiconductor Inc.

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