Electronic Design

Serial EEPROMs Answer Designers' Needs For More Point Storage

Available with a wide variety of interfaces and features, serial EEPROMs deliver nonvolatile memory in sizes from under1 kbit to 1 Mbit.

Traditional NOR- and NAND-type flash memories dominate most designer's minds when it comes to adding megabytes of nonvolatile storage to a system. But many cost-sensitive applications exist that don't need the high capacity or short access times they deliver. Filling the gap and providing a low-cost, small-format solution are bit-serial EEPROMs. These devices allow users to drop anywhere from a few dozen bits to 1 Mbit of nonvolatile storage into any system.

Although initially developed as a simple nonvolatile memory that could tie into a host processor over a two- or three-wire serial bus, serial memories have evolved into feature-rich devices. They come in versions that offer 8- or 16-bit word widths, which are sometimes switchable between organizations. Other highlights include password protection, block-write protection, and multiple access modes, as well as a multitude of other features and interface options to meet evolving system needs.

For most designers, storage endurance has become almost a non-issue. Through improvements in process technology and various types of error-correction schemes, EEPROM suppliers can now offer endurance ratings of anywhere from 100,000 to one million cycles. Guaranteed data-retention times range from 10 to over 100 years.

As many of the applications are in handheld, battery-powered systems, these serial EEPROMs must be physically small and consume next to no power. Long gone are the days when an 8-pin mini-DIP was considered small. Today, the thin, shrink small-outline package (TSSOP) offers the best economy for small board areas. But even smaller packages like the 5-lead SOT-23 are being put to work, delivering significant board-space savings. Last year, Microchip squeezed a 1024-bit I2C-compatible serial EEPROM into a SOT-23, which measures just 3 by about 1.5 mm (Fig. 1). The package saves 70% of the board space versus a package such as the 150-mil, 8-lead SOIC, and 50% against an 8-lead TSSOP.

Packages are growing smaller still. In a joint development announced last year, Xicor, in conjunction with ShellCase Technology, developed a chip-scale package that promises board-space requirements no larger than the area of the chip itself (perhaps 1 by 2 mm). In the next year or more, expect to pay a premium for this type of packaging. The initial manufacturing costs are high, but the package does hold the promise of lower cost once it's in volume production.

Also in the past are the times when a 5-V-compatible device would fit all system needs. A wide range of operating voltages are now used by the systems being designed. The EEPROMs must be able to operate from supply voltages as low as 1.8 V. The chips also must draw very little current—typically 1 mA or less when reading or writing data, and just a few microamps during standby.

Just about all of the serial-EEPROM suppliers have developed families of devices that are optimized for various operating-voltage ranges. Typically, they fall into 1.8 to 5.5 V, 2.5 to 5.5 V, 4.5 to 5.5 V, or some similar assortment. Even within one range, many companies create further subcategories for low and ultra-low power classifications. The designer gets a multitude of product options from which to select and optimize the final system design.

When first released over a decade ago, serial EEPROMs typically offered a simple two- or three-wire serial interface and capacities of a few hundred to a few thousand bits. Part of that limitation was due to process technology, but the serial protocol also created an artificial limit of about 16 kbits. The blame for that falls on the single-byte address that was used in the original MicroWire and I2C buses. Enhancements to the protocol extended the address capability to 2 bytes and beyond so that chips with megabit capacities can be accessed.

Currently, the basic interfaces are the same and small-capacity devices are still in great demand. But thanks to improvements in process technology, higher-capacity devices are readily available. Chips with capacities of up to 256 kbits are in mass production. Still higher-density versions, with 512-kbit and 1-Mbit capacities, are on the drawing board. They're expected to sample later this year.

The serial interfaces that tie the memories to the host system are changing to meet multiple system needs. MicroWire, the simple three-wire interface created by National Semiconductor Corp., Santa Clara, Calif., was the first of the serial buses. Its simple protocol and structure employed a serial clock line and both serial-data input and serial-data output signals. The company used MicroWire as an expansion bus on its microcontrollers. Various peripherals, such as memory or an analog-to-digital or digital-to-analog converters (ADC or DAC), could then be added very inexpensively and without requiring relatively scarce parallel-port pins. That product line is no longer offered by National Semiconductor. The products were transferred to Fairchild Semiconductor and are now part of that company's serial-EEPROM line.

At about the same time that National created MicroWire, Philips developed a chip-to-chip serial bus of its own. Requiring only two wires to handle clocking and serial-data transfers, the Inter-IC bus is what's now known as I2C. It was initially intended to move data and control information between the different chips of a multi-chip system, such as the main circuit board in a television receiver. The interface only requires a serial clock line and a bidirectional data line. The state of various bits sent to the memory in the first byte gives the device its instruction (read or write, for example). It also provides the address so that the proper location on the chip can be accessed. The next byte transferred contains the data (either read from or written to the memory).

Meanwhile, Motorola Inc., Austin, Texas, developed a three-wire, synchronous serial peripheral interface (SPI) for its microcontrollers as an alternative to the RS-232 asynchronous UART. In the early 1980s, the UART on most microcontrollers was limited to top speeds of only a few hundred kbits/s. From there came the need for a higher-speed serial interface like SPI, which could operate at data rates of 1 Mbit/s and faster. Initial SPI buses could handle data at a minimum of 1 Mbit/s. Still faster versions operating at up to 5 MHz weren't far behind.

Today, versions of the SPI bus that run at clock rates of up to 10 MHz are integrated on some serial EEPROMs. The higher-speed interfaces are needed, both to deal with the higher-capacity memories and to improve overall system performance. As densities go up, so do the overheads in accessing the data. Longer command and address sequences must be shifted in, and 8- or 16-bit data words must be shifted out. At the older clock rates—for example, 1 MHz—shifting in a command word, a 16-bit address, and then 16 bits of data would take over 40 µs (not counting the write time). With a 10-MHz clock, just 4 µs are needed.

Although this lower overhead time doesn't have a huge effect on system throughput, it can significantly impact system power consumption. That's especially key for all the portable systems. It may seem contradictory to say run faster and use less power. But in this case, by clocking the memory faster, data can be transferred in less time and the rest of the system can be powered down. The overall amount of power consumed by the system is reduced, versus running the entire system at the slower clock rate while the data is transferred.

Not only are the basic two- and three-wire interfaces still in wide use, but some of their variations are offering designers options that can reduce data-transfer overhead. A few devices, from companies such as Atmel, include a data-streaming mode that permits data bytes to sequentially stream out of the chip after a starting address is loaded. There's no overhead for transferring a new address for each data word.

The actual mode in the company's AT93Cxx family works like this: Upon receiving a read command and an address, the Data Out pin comes out of the high-impedance state. It sends an initial dummy zero bit, and then begins shifting out the data addressed (MSB first). The output data bits toggle on the rising edge of the serial clock signal. After the initial data word is shifted out, the Chip Select line remains asserted with the Serial Clock line continuing to toggle. The memory automatically increments to the next address and shifts out the next data word.

As long as the Chip Select line is continuously asserted and the serial clock line keeps toggling, the device will keep incrementing to the next address automatically until it reaches the end of the address space. At that point, it loops back to address 0. In the sequential read mode, only the initial data word is preceded by a dummy zero bit. All subsequent data words follow without one.

Despite these various bus options, work at memory suppliers is ongoing to create serial interfaces to improve overall flexibility and performance. Xicor's development, dubbed the MicroPort Saver, goes so far as to eliminate the need for the host to have a dedicated serial interface. The memory chip can tie into any software-controllable pins on the host. The system designer has more flexibility, because many higher-end processors don't include an SPI, I2C, or other dedicated serial interface.

In lieu of a serial clock line, the MicroPort Saver uses the Chip Enable as a clock and one of the host-memory-bus data lines as the Data Input/Output line (Fig. 2). The device can interface to most processors without any glue logic, simplifying system design. Writes and reads are controlled by the Write Enable and Output Enable lines. When the memory chip is selected, each read or write operation on the data bus is interpreted as a single bit in the serial-interface protocol. The interface scheme is fully static and can be interrupted at any time for the host to perform other bus activities.

It'll be a while before this interface is in widespread use, but its ease of implementation portends a promising future. In the meantime, the SPI interface has grown extremely popular. It's available on various embedded processors offered by Motorola and many other companies. With versions of the SPI bus capable of operating at 10 MHz, handling the latest high-density serial EEPROMs should be a simple matter.

Most previous serial buses operated at clock speeds from 100 kHz to about 1 MHz. For many applications, such speeds are still well within performance requirements. When it comes to real-time user interfaces, however, most users won't perceive response delays of 200 ms or less. But delays longer than 200 ms may make system responses seem sluggish. Or users could end up pressing buttons more than once because the feedback response would be slow. So higher clock rates can improve system performance. By clocking data at 10 MHz, responses will appear instantaneous.

Higher clock speeds aren't the only way that serial-EEPROM designers are trying to improve system performance. By employing page registers on the chip, it's apparently possible to speed write operations. Just about every supplier of serial EEPROMs quotes a write time of about 5 ms per byte for individual byte writes. By using the page register to accept multiple bytes at the bus speed and then write all of them simultaneously, they can considerably reduce the overhead time required for storing data. Page registers range in size from about 4 bytes on the smaller EEPROMs to about 128 bytes on the larger devices.

Aside from trying to move data faster, EEPROM manufacturers offer devices that include features to improve system performance. Examples include Schmitt-trigger inputs to minimize false switching, block-write protection, and password protection.

Password and block-write protection are two important aspects in which designers of networking and communications systems have a vested interest. Various levels of security are available on the chips from EEPROM suppliers. Xicor includes 64-bit password security on its X76F102. The 1024-bit device contains one 112-byte storage array and a 32-byte password storage array that holds two 16-byte user-programmable passwords (one for reads and one for writes). Also included is a retry-counter register, which keeps track of the attempts to access the secured array. If eight attempts are made with invalid passwords, the counter will activate the on-chip erase logic and erase the contents of the main storage array (Fig. 3).

Versions of the X76Fxxx secure serial flash memory are available with capacities up to 8 kbytes. The largest device, the X76F641, can have up to five 64-bit passwords for read, program, and reset control. All of the devices are available in either an 8-lead SOIC package or in a smart-card module.

Secure data products also exist in the form of code-hopping devices. They're employed by the automotive industry for car locks and by other industries for secure access. Microchip, for example, offers a family of KeeLoq encoder and decoder chips that include programmable encryption keys of 64 bits. Seed lengths go from 32 to 60 bits.

When data doesn't have to be secured, but just protected against overwriting, many designers will employ the write-protect capabilities available on most serial EEPROMs. Some devices offer full-chip write protection. Once data is stored, no alterations can take place short of erasing the entire chip. Other, more flexible solutions provide block-write-protect capabilities, which protect one or more sections (blocks) of the memory array once the initial data is written into the block.

Data-Protection Options
Examples that are serial SPI-compatible devices are the M95256 and M95128 from STMicroelectronics (Fig. 4). The 256- and 128-kbit chips offer both hardware and software write protection, a 40-year data-retention guarantee, and an endurance of 100,000 write cycles. Through 2 bits set via software control, the chips can be set to protect none of the memory, the upper quarter, the upper half, or all of the storage array. In the hardware-protection mode, the data bytes in the protected area as well as the contents of the status register are write protected.

A similar capability is available on the 128-kbit X24128 from Xicor. The I2C-compatible memory includes a block-lock capability that resembles the chips from STMicroelectronics. It also includes a 32-word page-write capability, a data-retention guarantee of 100 years, and an endurance of 100,000 cycles.

Along with pure memory functions, a number of companies have leveraged the ability to integrate small amounts of EEPROM storage on a chip with other functions. The result is a wide variety of peripheral support functions: digital potentiometers (DACs with EEPROM-based data-input registers) that remember their last setting, configuration switch replacements, and specialty devices that target markets such as the PC industry.

Check out the mixture of logic and EEPROM in the chip developed by Philips Semiconductors to support Pentium II chip sets. The PCA8550 combines a 4-bit 2:1 multiplexer and a 1-bit latch (Fig. 5). This device replaces mechanical configuration jumpers and switches with a simple-to-configure memory to speed motherboard setup and reduce potential damage from handling.

Housed in a 16-pin SO package, the chip is programmed via its I2C serial bus using a 2-byte sequence. The first serial byte transmitted to the chip contains a 7-bit address and a 1-bit command (Read/Write). This data determines the direction of the data transfer from the chip's nonvolatile register to the host (Read), or from the host to the chip's nonvolatile register (Write). The second byte holds data bits. Depending on the state of the command bit, these bits will supply data to the 5 EEPROM bits that control the multiplexer and latch. Or, they'll capture the state of the EEPROM bits and return that information to the host.

The chip provides a 4-bit 2:1 multiplexer and a 1-bit latch, all controlled by a 5-bit internal, nonvolatile register. With an override pin, the system can force all outputs to logic 0, which aids in trying to perform hardware diagnostics. A write-protect pin lets the host enable/disable I2C writes to the register. The primary function of the 4-bit 2:1 multiplexer is to select either a 4-bit input or data from a nonvolatile register and drive this value onto the output pins. One additional non-multiplexed register output is provided. During I2C writes to the nonvolatile register, that output gets latched to prevent output-value changes.

A Mix Of Capabilities
Digital potentiometers also offer a blend of functionality. A DAC delivers the desired analog output, which is used in turn to control the volume in audio applications. The digital input to the converter comes from a simple 4-, 6-, or 8-bit nonvolatile register that's loaded with the desired value via a serial interface. Several companies list such products, which are available in single, dual, or quad implementations. Catalyst, Dallas Semiconductor, and Xicor are some of the main suppliers.

Microprocessor supervisory circuits with on-chip EEPROM are a novel offering from Catalyst. Aside from precision power-supply monitoring, a watchdog timer, and five programmable reset thresholds, the chips come with 2 to 16 kbits of on-chip EEPROM. They combine two commonly needed functions in microprocessor systems onto a single chip, simplifying system design, further reducing board space, and lowering system cost. Designed to tie into I2C-compatible systems, the CAT24Cxxx series can clock at 400 kHz. Another option is to include a 16-byte page-write buffer to speed data storage.

This broad variety of EEPROM serial memories gives designers a wide latitude for selecting the best solution for their systems. And it only promises to improve in the future, as process technologies and design tools allow the creation of even more versatile products.

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