The push is on for IC packages in smaller form factors, not only length- and width-wise, but also height-wise. Hence, the term “3D ICs.”
Smaller form factors require greater density, and that means stacking chips and boards on top of each other in a 3D form. As ICs downsize from quad flat packs (QFPs) to ball-grid arrays (BGAs) and further down the line, fewer stacks and external I/Os are needed (Fig. 1). Many semiconductor IC experts warn that a looming interconnect crisis will emerge within a year or two, with timing delays and higher resistances in aluminum and copper interconnects caused by downward chip scaling.
Besides memory and logic, consumer electronics now integrate CMOS image sensors. Microprocessors and DSPs are sure to follow. Gigahertz and terahertz performance frequencies aren’t too far off for future consumer and other massmarket products. And when microelectromechanical-systems (MEMS) ICs join the 3D fray, packaging challenges will become even tougher.
These challenges, triggered by cramming more functions onto ever-smaller IC die, include choosing the right packaging materials, developing a cost-effective interconnect technology, determining how efficiently heat is being managed, and the growing need for better electronic-design automation (EDA) tools.
SIPS IN THE LEAD
There’s no shortage of novelties in IC packaging, with waferlevel packages (WLPs), chip-scale packages (CSPs), multichip- modules (MCMs), and multichip packages (MCPs), as well as system-in-package (SiP) and package-on-package (PoP) technologies.
According to the International Technology Roadmap for Semiconductors (ITRS), two of the most attractive approaches for 3D packaging are system-on-a-chip (SoC) and SiP methodologies. SiPs are basically MCMs with higher packaging densities and better time-to-market advantages.
W.R. Bottoms, chairman and CEO of NanoNexus, envisions packaging innovations as the answer to the difficulties that will be encountered in scaling down CMOS ICs as envisioned in Moore’s Law. Bottoms also is the chairman of the Packaging Technology Working Group for the International Electronics Manufacturing Initiative (iNEMI) Roadmap and the ITRS Roadmap for Assembly and Packaging.
Among the numerous concepts developed for 3D SiP packaging, the use of WLP has emerged as a notable trend, says Bottoms (Fig. 2). WLP allows for the packaging of both single- and multi-die devices, wherein all elements of the package are within the boundaries of the die. Also, all packaging processes are performed before a wafer is singulated into individual circuits.
SiPs don’t replace SoCs, which represent a high level of on-chip integration. Instead, they may complement each other. A complex- function SiP may contain one or more SoCs. Or based on the application, an SoC may be preferable to a SiP.
POP TARGETS CONSUMER PRODUCTS
Consumer electronics are among the biggest drivers for high-density IC packages. The PoP concept, a subset of the SiP concept, is proving attractive in this market. Typically, a PoP involves stacking discrete memory ICs and discrete logic ICs, in BGA and microBGA packages, on top of one another.
While IC manufacturers often stack IC chips of different functions into a single package, the PoP approach is valuable in terms of configuration flexibility for mobile phones, digital cameras, and PDAs. That’s because each of the PoP layers can be can be fully tested prior to stacking for greater yields in the finished product. The cost savings are key for consumer electronics applications.
Tessera Inc. honed the PoP approach via its µZ ball stacking for BGA packages (Fig. 3). IC die are placed face down on an elastomer attachment site furnished on the substrate base material and electrically connected through a rectangular slot using conventional wire bonding.
The PoP’s carrier or substrate typically extends outward beyond the perimeter of the die. This allows the substrate to accommodate the assembly of die from different manufacturers with different sizes. It also ensures compatibility with future die shrinks.
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Yet the PoP approach raises some reliability and testing challenges in stacking memory chips on top of logic chips, as was discovered by Stats ChipPAC. This is especially the case for lower-cost NAND flash memory, which is rapidly replacing conventional NOR flash memory.
Stats ChipPAC points out that the PoP approach must be more carefully controlled to minimize substrate warpage or deformation caused by temperature changes during reflow soldering. The degree of polymerization during the post-handling process can be helpful since it attenuates the effects of internal residual stresses, which are a factor in substrate warpage.
The company recommends using smaller solder balls on the top pad of the bottom logic layer in a PoP while minimizing the amount of solder paste. In addition, PoP users should be aware that testing challenges still remain for PoPs in terms of lower costs, test-platform capabilities, and test strategies.
Another drawback to the PoP approach is the rising costs of BGA package substrates, which now account for most of the total PoP package cost and become even pricier as more BGA-based layers are used in a PoP. Alternative substrates are required for BGAs as electronic circuit performance levels increase.
Infineon Technologies partnered with Advanced Semiconductor Engineering to offer its alternative embedded waferlevel BGA (eWLB), which promises excellent electrical and thermal performance and maximum connection density. It features higher integration levels for a given package size with an almost infinite number of contact elements.
According to Infineon, eWLB achieves a 30% reduction in dimension compared to conventional leadframe laminate packages. All operations are performed in a highly parallel concurrent manner at the wafer level.
To further advance PoP technology, Amkor developed a through-mold via (TMV) method that offers several advantages for next-generation mobile multimedia products over conventional PoP approaches. With TMV, designers can form fine-pitch tall solder joints with minimal risk of shorting. It also offers higher levels of integration using passives or stacked die, better basepackage flatness, and higher assembly yields.
TMV is based on a standard fine-pitch BGA (FBGA) package with wire-bond, flip-chip, or stacked-die interconnections. After molding, a blind via is created through the mold compound, which exposes PoP bond pads on the package substrate’s top metal layer. The vias are partially filled with a conductive material before final processing, resulting in a fully molded FBGA package with a conductive blind via PoP interface.
THE INTERCONNECT HURDLE
Every major IC manufacturer and semiconductor equipment maker is investigating how it can stack chips using TSVs to satisfy present and future demands. It’s currently more expensive to implement TSVs for interconnections than conventional wire bond, but the cost gap is narrowing with flash memory. Within four or five years, a significant percentage of 3D ICs will use TSVs.
An interposer system can also help reduce the cost of interconnecting high-density stacked packaging. Interconnect Systems offers a fan-out interposer that allows microBGAs with ball pitches under 1 mm to be used, essentially converting microBGA packages to larger-pitch packages suitable for larger and thicker printed-circuit boards (PCBs). As a result, the latest and most cost-effective ICs can be employed without increasing the PCB’s system cost. Yet this approach is only useful if the larger size of the interposer is acceptable to an application.
BGA and microBGA problems intensify as the solder-ball diameters shrink with greater packaging densities. Solder-ball smoothness and oxidation effects are exacerbated as their diameter and roundness dimensions become smaller. The patented Multicore Accurus process from Henkel Corp. mitigates many of these problems, taking at least 100 measurements per solder- ball sphere to ensure proper and thorough solder-ball deposition.
Tessera achieved success using TSVs with its Shellcase MVP wafer-level chipscale packaging (WLCSP) technology, which is available for licensing in cavity and non-cavity formats and leaded and lead-free bumps (Fig. 4). “Not only does Shellcase MVP decrease overall manufacturing costs with the added benefit of supporting legacy systems, but it also provides a longer-term manufacturing roadmap with its support for 3D stacking of image sensors and other ICs such as DSPs and flash memory,” says Bents Kidron, Tessera’s vice president of marketing.
Before TSVs see widespread use, some technical issues must be tackled. One of the stiffest challenges is developing a costeffective via fill process that isn’t expensive and time-consuming. Tools are needed for double-sided lithography. So are a means of achieving precise front-to-back wafer alignment to create the TSVs, the ability to handle thinner wafers, and practical methods for wafer or chip-to-chip bonding.
Also, a backside lithography step is needed if TSVs are etched after wafer thinning. Typically, a wafer is bonded prior to being thinned for mechanical support. To create the TSV etch mask, optical alignment is necessary with reference to alignment keys in the bond interface. At present, metalbased adhesive and direct-bonding are preferred for 3D interconnects.
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IBM, the EV Group, NEXX Systems, Surface Technology Systems, SUSS Microtech, and Tezzaron are investigating 3D TSV interconnects. Other interested organizations include the Fraunhofer Institute of Technology, Georgia Institute of Technology, IMEC, Taiwan Semiconductor Manufacturing Company (TSMC), and Tohoku University.
TSV manufacturing proposals include chip-to-chip, chip-to-wafer, wafer-towafer, TSV first, TSV last, and self-assembly production methods. None has seen wide-scale adoption, nor have the many competing TSV materials like copper-tocopper, copper-to-gold, and solder.
Working with Cubic Wafer Inc., Aviza Technology is proposing a die-to-wafer stacking technology that will produce TSVs with 15-µm diameters and 100-µm depths within a CMOS IC having 90-nm line features. The vias are formed by etching a 9-µm thick dielectric that consists of 40 layers. A deep silicon etch system next forms the TSVs. Ionized physical-vapor deposition (PVD) is then used to form a barrier and seed metal.
According to Aviza, this ionized PVD is better than a conventional PVD process because it allows TSV scallop depths of 0.4 µm and mask undercuts of 0.5 µm with 2.5 µm of tetraethyl orthosilicate (TEOS) material. Void-free copper plating completes the TSV. Aviza already has a Versalis fxP cluster system for 3D stacking that handles 200- and 300-mm wafers.
One challenge for SiP development is in the wireless RF arena, with the omnipresent mobile phone. Existing approaches that use ceramic packages or silicon passive components have proven costly and can’t always meet the high levels of integration often desired. An improvement for RF SiP substrates has come from a patented thin-film multilayer organic process developed by Rogers Corp. working with Jacket Micro Devices (Fig. 5).
The approach combines advanced RF circuit materials based on liquid-crystalline polymers (LCPs) and ceramic-filled polytetra-fluorethylene (PTFE) composites, coupled with novel processing and circuit topologies. To maximize integration levels, the materials feature low loss at high frequencies, a stable dielectric constant, good laser micro-via capability, low moisture absorption, and good thermal stability. The end result is high performance and high reliability.
At the chip-scale level, Avago Technologies announced a breakthrough in packaging that brings wireless chip micro-miniaturization and high performance to new levels. The company claims its WaferCap is the industry’s first semiconductor-based gallium-arsenide (GaAs) CSP FET (Fig. 6). It provides the lid while the basic wafer incorporates the active device.
The pseudomorphic-high-electron-mobility- transistor (pHEMT) is a lownoise device with a frequency range of 500 MHz to 12.5 GHz, with the potential to reach 100-GHz operation. The surfacemount package has the same dimensions as an 0402-size component, measuring 1 by 0.5 by 0.25 mm, and can reduce the space it requires on a PCB by more than 50%.