Electronic Design

Simulate Multicore Systems Before Silicon

Virtutech's Simics will bring Freescale's new architecture to life before the hardware is in your hands.

It's still a bit early to start expounding on Freescale's new multicore Power architecture-based communications platform (see the figure). But with the help of Virtutech's Simics development platform, Freescale developers can access functional platforms well in advance of silicon.

Virtutech has worked with Freescale on platform simulation for some time, including the MPC8641D dual-core embedded processor (see "First Freescale Dual-Core Simulation" at www.electronicdesign.com, ED Online 12425).

The dual-core MPC8572E is the latest chip supported by Virtutech's Simics platform. It includes both a slower cycle-accurate simulation and a faster functional version. It's also possible to switch between modes. As a result, developers can quickly run through a bootup process in the functional mode and switch to cycle-accurate mode to check out a new device driver.

The latest support simulates the full development board for the MPC8572E. Simulation can deliver significant advantages such as improved debugging in addition to being available early in the design cycle. In fact, Freescale is using this type of simulation to help design its next-generation platforms.

Simulation shines in debugging. Simulations can expose aspects of the hardware that will be unavailable or limited on the actual hardware. For example, simulated trace information may provide access to cache status that isn't usually available in a hardware trace. Likewise, Virtutech's Hindsight debugger supports reverse execution tracing.

Freescale's architecture supports up to 32 e500-mc processor cores tied together with other hardware via the CoreNet fabric. The fabric includes communication and accelerator devices, such as the QUICC (QUad Integrated Communications Controller) engine.

The CoreNet fabric isn't full mesh, but it does support multiple, concurrent transactions on a shared, arbitrated bus. Also, the fabric hardware maintains cache coherency.

Processor cores may have their own L1 and L2 caches, and a system L3 cache can be supported, too. Information moving through the fabric is self-routing and handles processor virtualization support. The design can manage multicast and broadcast transactions.

With the data-path resource management (DPRM) accelerator, a variety of schemes can be used to direct data to memory, processors, or accelerators. It allows for the implementation of intelligent load balancing by steering data according to dynamic workload and resource availability, such as memory buffers and accelerator usage. The DPRM effectively manages queues of pointers with a prioritization scheme for selecting work to perform.

Software developers will need to experiment with the advanced CoreNet routing and DPRM's management features to exploit them. Access to the systems via simulation should prove to be invaluable.

Details of Freescale's new architecture are still being revealed. In the meantime, it's possible to see what the collaboration between Freescale and Virtutech has wrought using the simulations of shipping hardware.


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