The supreme dominance of Moore's Law in driving semiconductor technology is coming to an end. MOS transistor gate lengths have shrunk from several micrometers in the 1970s to below 0.1 µm (100 nm) today, while the number of transistors on a device has increased from hundreds to hundreds of millions.
But the application needs are changing, and with them the development of IC technology. While CMOS scaling was essential to the growth of PCs during the last 20 years, the requirements of high-speed communications that converge data, voice, and video into a single digital stream are driving today's technology. The PC era is behind us and the Internet era lies ahead.
Internet appliances de-pend on DSPs and analog functions that interface DSPs to the real world. While Moore's Law scaling is important to the future of these systems, it tells only half of the story. Just as significant in the long run is achieving system-on-a-chip (SoC) integration of digital and analog/RF functions.
Any solution must reduce overall system costs, including board space, power consumption, development time, manufacturing assembly, and test. Die costs by themselves dictate that high-volume solutions must be implemented in CMOS.
Future CMOS generations face grand challenges to continue scaling. Today, transistor gate lengths are considerably smaller than the wavelength of the radiation used to expose them. Gate lengths of under 100 nm are routinely printed using 248-nm light, and the problem is getting progressively worse. Another challenge of scaling is the gate insulator. Now less than 2 nm and only a few atomic layers deep, the SiO2 insulator, the mainstay of the industry for decades, will be replaced over the next few years by a "hi-k" insulator.
Thus at the end of this decade, Moore's Law scaling will stagnate. When this happens, continued SoC integration will drive growth in IC capability. But integrating analog/RF functions in CMOS poses its own challenges. Unlike the uniform transistors of digital logic, different analog/RF functions require different types of transistors with unique specs, and they typically don't scale as readily. Some analog/RF functions are extremely sensitive to the noise from high-frequency digital clocks and must be electrically isolated on-chip. Also, many of the passives, especially for RF, are difficult to implement in CMOS.
Reduced voltages further complicate the design. Now, digital core voltages are as low as 1 V, and I/O voltages are falling. But analog functions often need the dynamic range afforded by higher voltages to minimize noise. Applications like microphone drivers demand fixed power levels, so lower voltages must be compensated for by increased current. Plus at low voltages, switches lack drive current to achieve the required speed.
Today's digital wireless phones typically use more than 200 discretes and passives and about six ICs, which include a DSP, microcontroller, analog baseband, RF, and power-management chips. SoC integration will require high-density logic, embedded RAM, nonvolatile Flash or FeRAM, analog CMOS, and extended-drain CMOS that can withstand up to 10 V. RF functions will require integration of passives. Despite barriers to packing such diverse functions, SoC integration is on track to enable single-chip wireless phones within the next three to four years.
Wireless handsets are currently the strongest drivers of SoC technology because cost, space, and power consumption are at a premium in these high-performance systems. Just as Moore's Law enabled PC proliferation in the PC era, SoC integration will drive the Internet era.