Taking A Peek Under The Hood Of Your Spice Circuit-Simulation Engine

DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2.

In today's quest for simplicity in "ready-to-use" EDA tools, understanding what's under the hood of a Spice circuit-simulation engine can be helpful, particularly for designs that challenge the conventional limits of Spice. Analog-centric designers will get the most out of Spice simulation by combining their knowledge and experience with an understanding of how their Spice design tool works.

Stepping back to Analog 101, Spice (Special Programs with Integrated Circuit Emphasis) is essentially an equation solver, in compliance with Kirchhoff's Current Law (KCL). The KCL matrix is modified by Spice to analyze the current through voltage sources, and with digital components (e.g., as with XSpice), it uses state variables in model extensions. For linear time-invariant circuits, the equation matrix creates a unique solution. Nonlinear circuits and operations involving integration require inserting a Norton equivalent circuit with the large-signal current summed into the matrix's right-hand side (RHS) and the small-signal conductance summed into the matrix.

That summation process is applied to the "matrix stamp" of a Spice model. Interestingly, during a Spice simulation, each model sums its contributions without knowing what the other models are doing.

The article discusses the Spice options for operating-point control to attain successful convergence and transient simulation control. Design tips are provided with various options to help make the process more efficient.

HIGHLIGHTS:
Spice Options And Design Tips For Operating-Point Control	Key Spice options and considerations are given for those trying to achieve successful dc operating-point convergence. Operating-point convergence refers to the initial stable solution for all of the dc steady-state voltages.
Spice Options And Design Tips For Transient Simulation Control	Transient simulation refers to the large-signal analysis of a design, as would be performed using instruments like an oscilloscope, a signal generator, and a dc power supply on a breadboard design.
Behavioral Hysteresis Comparator	Figure 7 shows the comparator switching with default Spice options (a). It has a rise time equal to the Spice time step when passing the switching threshold (b). Performing the same simulation with VSECTOL=50n makes the vref signal switch from 0 to 5 V in less than 10 ns (c).
Initializing Complex Circuits	The preferred method for initializing these circuits, shown in Figure 8, is to use switches that apply initial conditions at time = 0, then remove the ICs when time > 0. Here, the technique is applied to a simple R-L-C circuit.

Full article begins on Page 2

In today’s quest for simplicity in “ready-to-use” EDA tools, understanding what’s under the hood of a Spice circuit simulation engine can be helpful, particularly for designs that challenge the conventional limits of Spice. Analog-centric designers will get the most out of Spice simulation by combining their knowledge and experience with an understanding of how their Spice design tool works.

Stepping back to Analog EDA 101, Spice (Special Programs with Integrated Circuit Emphasis) is essentially an equation solver, in compliance with Kirchhoff’s Current Law (KCL). The KCL matrix is modified by Spice to analyze the current through voltage sources, and with digital components (e.g., as with XSpice), it uses state variables in model extensions. For linear time-invariant circuits, the equation matrix creates a unique solution. Nonlinear circuits and operations involving integration require inserting a Norton equivalent circuit with the large-signal current summed into the matrix’s right-hand side (RHS) and the small-signal conductance summed into the matrix.

Referring to Figure 1, the above summation process is applied to the “matrix stamp” of a Spice model. Interestingly, during a Spice simulation, each model sums its contributions without knowing what the other models are doing. When the diode anode is node K and its cathode is node L, the rows and columns of both K and L have the small-signal conductance summed into their matrix positions as shown. The large-signal current is summed with appropriate signs into the RHS.

Spice then iterates this solution to solve the nonlinear circuit equation. It’s worth mentioning that the simulator can’t distinguish linear and nonlinear circuits, so it will iterate linear circuit equations as well. Note that the basic KCL rule is: The sum of the currents at a node is constant. However, certain linear circuit equations may fail to converge if the RHS vector isn’t a constant. In this case, there’s no guarantee of convergence (state of complete matrix resolution).

Let’s critique a nonconvergence example. Note the transformer description in Figure 2 and its modified-nodal-admittance (MNA) matrix. Current is transformed from the input side (left) to the output side (right), while voltage is transformed in the opposite direction. These equations force the output power to equal the input power. The model also is useful for any power-conserving operation. In the third equation, the current at B4 is .5*IR1 (yellow). It must remain on the RHS because IR1 isn’t a matrix variable.

For this circuit configuration, v2 grows at each iteration, as shown in the Table. Clearly, the solution isn’t converging; v2 is alternating in sign and its magnitude is growing rapidly to infinity. However, if the model’s input and output were reversed, then the solution would have converged.

Next, consider an example of valid convergence (Fig. 3). The input current is sensed through a voltage source instead of a resistor. The current through the voltage source is a matrix variable. Here, a Spice3 arbitrary source by way of a B-element (Behavioral, Berkeley Spice) saves the variables and their derivatives. It then uses that information to move any RHS components using those variables back over to the matrix during the load operation as shown. With this minor change in the model, the circuit is made to converge without the need for any iterations. Importantly, one should consider B-element equations that only use matrix variables. One can still write equations with variable RHS values, but as was previously shown, it’s unwise to rely on the solution iterations to converge.

Back to Spice. To handle nonlinear algebraic equations, Spice simulators perform what’s known as a Newton-Raphson iteration. The linearized matrix of the diode shown in Figure 1, for example, is solved, plus a new operating point and its small-signal equivalent admittance are found. The process is repeated until reaching a stable solution. Figure 4a shows a test circuit using a diode, while Figure 4b shows how the equation is successfully iterated. Modeling a diode voltage as a function of current follows suit to real-world design, because that’s the typical procedure for estimating a diode’s operating point. Remember that a silicon diode’s forward drop ranges from 0.6 to 0.7 V for a large range of current.

Earlier on, the problem of finding a stable solution for this circuit used the equations formulated with current as a function of voltage (Fig. 5). You can see from inspection that the initial trial would place nearly 5 V across the diode, resulting in 8.348e+069 A. The next iteration would produce nearly the same result. Successively, it would take forever to walk the solution back to the correct answer. Luckily, Spice3 quickly recognizes this convergence problem and tries some interesting tricks to make even this ill-conditioned equation work.

The dc iteration limit (ITL1) defaults to 100 iterations. When it’s exceeded, the simulator employs a protocol called, “Gmin Stepping,” and if necessary tries another procedure called, “Source Stepping.” Gmin is a Spice option based on the smallest possible conductance. Spice3 begins by setting the number of steps to 10, then computes the diagonal offset as (Gmin *10^numSteps). For the default, Gmin = 1e-12, and the initial offset is 0.01. That corresponds to a 100-W resistor to ground on the diagonal nodes. If convergence fails on the first step, then the simulator signals, “Gmin Step failed.” In such a case, one might increase the numGminSteps or increase Gmin.

Most Spice vendors have modified these algorithms to improve their performance. In Figure 3, we saw that a 100-Ω resistor across the diode initialized much closer to the correct solution in the example. The offset is gradually removed, and if on its final removal the circuit converges, the job is done. As previously mentioned, Spice3 otherwise engages its source-stepping matrix-resolving algorithm. With source stepping, all voltage and current sources are set to zero and stepped up to their final values using the number of steps as specified with ITL6.

For example, if you set ITL1 = 50 in Figure 5, then Gmin Stepping fails. Source stepping will in turn walk the solution up the I-V curve from V = 0 to create convergence. Depending on the vendor, Spice works pretty hard to make even poorly constructed models converge. Most modern Spice simulators employ variations of the described operating-point convergence methods and have fine-tuned the algorithms.

Design Tip: When building specialized models, you may need to keep the accounts option turned on (.OPTIONS acct) and keep an eye on the operating-point iterations.

Spice Options and Design Tips for Operating-Point Control: Recall that operating-point convergence simply refers to the initial stable solution for all of the dc steady-state voltages. This solution is needed for successive analysis types to be invoked, e.g., ac, dc-sweep, transient, etc. Most analog and mixed-signal designs simulated by today’s Spice don’t require “fiddling” of convergence parameters. But there are always some designs that stress the normal default settings and algorithms enough to where tweaking the settings may become necessary.

The following are some key options and considerations in their use for successful dc operating-point convergence:

Gmin (default is 1e-12): Gmin sets a minimum level of conductance in a design (see previous discussion with respect to its use in Gmin stepping). It’s also used within various models to eliminated divide-by-zero errors. Typically, divisions have Gmin added to the numerator and the denominator as follows: A/B approaches (A+Gmin)/(B+Gmin). This approach yields an answer for B = 0 and both A and B = 0. The odds of B = -Gmin are greater than 1 in 248 (2.8e+014). This is because the 64-bit floating-point mantissa is 48 bits long. On the other hand, the odds of having a value of zero are extremely high because many variables during the Gmin process are initialized to zero.

Design Tip: If using B-element equations, you can use Gmin as a parameter or insert a reasonable value (i.e., 1u \[“A” unit of measure or “B” unit of measure\]) into your divisions.

RELTOL (default = .001): ABSTOL (default = 1e-12): VNTOL (default = 1e-6): These are convergence parameters used after each Newton-Raphson iteration to decide whether or not each node voltage or branch current has converged. If “val” is the value just iterated and “prev” is the previous value, the following logic is applied:
   a. Voltage: tol = abs(val) * RELTOL+VNTOL
   b. Current: tol = abs(val) * RELTOL+ABSTOL
   c. If abs(prev-val) > tol return(NONCONV)

These equations appear reasonable for a circuit that’s working under usual conditions. But for the exception, Spice can reach some very extreme values. As abs(val) approaches infinity, the tolerance gets very large and unacceptable values may appear to converge. You may encounter this condition, for instance, when attempting to float a section of circuitry. The floating-circuit node voltages become independent of Spice ground. The dc offset can get so large that a matrix solution becomes impossible. Of course, the answer to this example is to not float circuitry!

Modeling Consideration: The ABSTOL and VNTOL settings apply to every node voltage and branch current. You should scale specialized component models in a similar range. For instance, if you need to maintain accuracy for very small numbers—i.e., when time delay is a variable—then you should scale your model to compute the time delay in microseconds or milliseconds as the case may be. Alternatively, you can use normalizing B-elements to multiply the voltage or current to attain a result in the proper range. These tolerances are also applied when calculating the local truncation error (LTE) for time-step control.

RSHUNT (default not used): The RSHUNT value is connected from every node to ground. This helps track down singular matrix problems that occur when ideal capacitors are connected in series. Without resistors, there’s no unique solution for series capacitors. RSHUNT can also be used to converge problematic circuits. Making RSHUNT small enough should make almost anything converge. Figure 2 shows an example that can be made to converge by setting RSHUNT to 1 mΩ.

Design Tip: If using RSHUNT as a debugging tool, keep in mind that it could introduce errors in models that use high-impedance circuitry, such as integrators or charge amplifiers.
ITL1 (default = 100): This represents the dc iteration limit. Reducing ITL1 can move Spice more quickly to source stepping—an algorithm that resolves convergence to the next level.

Design Tip: For complex circuits, you may need to increase ITL1 up to 1000. Beyond that, you are likely to experience chaotic behavior and converge by chance.

ITL6 (default = 10): ITL6 holds the number of steps used in the source stepping convergence algorithm.

Design Tip: You may need to set this as high as 1000 for complex circuits. Alternatively, instead of increasing ITL6, you might want to use .NODESET (described later) to produce convergence during the initial Newton-Raphson operating-point iteration.

AUTOTOL (default not used): This debugging tool, unique to isSpice4, may be the answer when dealing with tougher convergence issues. It causes a table of VNTOL and ABSTOL values to be set up for each node voltage and branch current. Whenever a non-convergent situation arises, the table value is multiplied by abs(AUTOTOL). That process rapidly eliminates the troublesome nodes. If AUTOTOL is negative, the activity is reported in the “.out” file.
NODESET: This is not part of the .options commands. However, its use is important in steering the initial operating point solution to one of several stable solutions. Figure 6 illustrates how this works for a bistable circuit.

Spice Options and Design Tips for Transient Simulation Control: Transient simulation, of course, refers to the large-signal analysis of a design, as would be performed using instruments like an oscilloscope, signal generator, and dc power supply on a breadboard design.

METHOD: This parameter selects Gear or Trapezoidal integration. Gear works best for power electronics or other circuits that use inductors, especially when the inductor current is switched rapidly. Spice diodes with reverse recovery will snap off and cause numerical artifacts when using Trapezoidal integration.
MAXORD (default = 2): Selects the integration order for Gear
TRTOL (default = 7): TRTOL represents transient error tolerance. This is the factor by which Spice overestimates local truncation error (LTE), which is the estimate of integration error. Each component that uses the Spice implicit integration method computes the time step required to achieve the desired accuracy. The smallest time step from these calculations is used for the successive time step. If the required time step is less than the current time step, or if the Newton-Raphson solution doesn’t converge, or if the VSECTOL condition isn’t met, the time step is scaled back. Increasing TRTOL will increase the time step. This parameter was empirically selected to give the best performance over a wide range of circuits. It shouldn’t be changed. TRTOL also enables Intusoft’s IsSpice4 VSECTOL options to have hysteresis (discussed later).
ITL4 (default = 10): ITL4 sets the lower transient iteration limit. This may need to be increased up to 100 for complex circuits. If it must be set higher to achieve convergence, then you may be experiencing chaotic behavior. Thus, small changes in initial conditions could cause non-convergence.
CHGTOL (default = 1e-14): This parameter sets the maximum charge error, only used in the LTE calculation.

VSECTOL (default off): This convergence parameter is another that’s unique to IsSpice4. If VSECTOL is turned on, its value represents the maximum volt-second error for any node voltage. Node voltages for the next time step are predicted based on their history. The next time step begins with the predicted values. For instance, if the product of the time step and the absolute value of the difference between the iterated value and the predicted value are greater than VSECTOL, then the time step is scaled back. As previously mentioned, TRTOL is used to provide hysteresis in the decision making. The time step won’t be increased until the VSECTOL computed time step is TRTOL times greater than the current time step.

Advantageous convergence innovation: VSECTOL becomes necessary to get fast rise times from behavioral switching as illustrated by Figure 7. For the case shown, 278 time points were required to achieve the 10-ns resolution (Fig. 7a). Without VSECTOL, the maximum time step would have to be reduced to 10 ns, requiring 5e6 time points, which lengthens the simulation by a factor of 17,986 (Fig. 7b). The circuit shown in Figure 7a is a hysteresis switch that can be used to model undervoltage lockout (UVLO). The VSECTOL option will cause the IsSpice4 kernel to backtrack; that is, reverse time and back up to just before the switching event occurred as shown in Figure 7c. An R-C network is needed because the hysteresis is time-directionally sensitive; without the R-C network, the switch point can be incorrect.

BYPASS (default = on): This bypasses computation of model parameters when the input voltage and currents haven’t changed very much. The process speeds simulation.
RAMPTIME (default = off): When RAMPTIME is set, voltage and current sources will be ramped from 0 to their specified value in RAMPTIME seconds.
NOOPITER (default = off): NOOPITER skips the op calculation and goes directly to GMIN stepping.
MINSTEP (default = off): MINSTEP removes saved data points that lie closer in time to each other than the MINSTEP interval. This option reduces memory requirements for lengthy simulations, but aliasing of data can occur.
MINBREAK (default = off): Breakpoints will not be set to less than this value. Vaious models use breakpoints. For example, V and I sources will set a breakpoint at the end of RAMPTIME. Transmission lines will set breakpoints when a change in the propagated signal reaches the terminals. MINBREAK is most frequently used to reduce transmission-line computational overhead.

TMAX (default off): TMAX represents the fourth term in the .TRAN statement and can optionally be set to override the Spice automatic time-step algorithm. TMAX is frequently used in Spice2 and Spice3 for the simulation of switching power supplies. It can substantially increase in simulation time and memory. See use of VSECTOL (above) to eliminate the use of TMAX.

Design Tip with Transient Initialization: Ordinarily, the initial operating point for a transient simulation uses the dc operating point calculation. However, this technique doesn’t work for certain circuits. For example, Spice can alternatively direct the simulator to use initial conditions by way of the UIC keyword in the .TRAN statement. When invoked, the circuit is initialized using the IC=keyword in various models and .IC v(node)=value statement. Note, however, that UIC works for circuits that don’t employ subcircuit models.

When a subcircuit is used, the internal ICs (Initial Conditions) may not correspond to the ICs of the external circuit. For example, a positive op-amp output voltage may cause current to flow in an inductor. If you initialize the inductor current, then you must also figure out how to initialize the op amp properly. Otherwise, the inductor current may flow into an open circuit. Needless to say, this is a very difficult task because you may not know much about the internals of vendor-supplied models. Moreover, many state variables are private to models—for example, diode charge—so that you won’t be able to initialize everything. The following is a Spice3 script that can be used (in IsSpice4) to extract the initial conditions after a transient simulation has run to steady state:

* script to extract the final value from a transient simulation
* remove everything except the node voltages
set colwidth=1 
nv = nextvector(null)
while nv  null
Len = length(nv) – 1
if len > 1 
Printtext -n “.IC ”
printname nv 
printtext -n “=”
printval nv\[len\]
printtext
End
nv = nextvector(nv)
End

If used, there are some drawbacks. All of the instance current and power values must be removed because they can’t be initialized using UIC. The remaining script must be pasted into the User Statements window of the Simulation Setup dialog. For currents, you find the parts affected and fill in the IC=value. The preferred method for initializing complex circuits is to use switches that apply initial conditions at time = 0, then remove the ICs when time > 0. This is similar to what the old analog computers used to do. Figure 8 shows how this applies to a simple R-L-C circuit. The advantage of this technique is it sets the main reactive component ICs with pulse switches and lets Spice tend to everything else. The ICs were purposely set a little off to create something to analyze. The error between the initial and final value is just under 1 mµ. In comparison, if you use the previous script to find the ICs, the peak error is less than 7 mµ.