With timing-margin budgets changing so rapidly during an IC or pc-board design project, miscommunication of relevant information among design teams can create serious headaches. Timing-Designer 7.0, an interactive timing-analysis and diagramming tool, seeks to simplify the exchange of critical timing information. Users will be able to better manage the specification and analysis of high-speed interfaces in digital ICs and boards.
To handle growing design complexity, TimingDesigner 7.0 gives users the option to logically organize multiple timing-diagram components within one project. Components and blocks are arranged and displayed in a single tree with a summary list of all constraint violations in the project diagrams. Designers also can merge two diagrams from different components. This automatically creates an interface that accounts for component connectivity and manages signal duplication and propagation delays.
This release includes other enhancements. Designers now can localize library management for specific diagrams and their associated paths, avoiding time-consuming network access to large library repositories. Also, to simplify analysis and accelerate debugging, designers can designate the use of only minimum or maximum values for their diagrams (as opposed to both minimum and maximum) to perform best- and worst-case timing analysis.
TimingDesigner 7.0 is available now, with pricing starting at $2460. The tool is supported on the Windows, Sun Solaris, HP-UX, and Linux platforms.
Forte Design, Chronology Division