Electronic Design

Tool Optimizes FPGA/CPLD Assignments

With FPGA pin counts rising to 2000, and projections seeing that number balloon to over 3000 by 2007, a crisis of complexity is rising in pc-board routing. Routing pinouts for such complex devices has forced board-layer counts to 50 and higher. Add in the fact that a Xilinx Virtex II FPGA can support up to 61 different I/O standards across nearly 1000 user-defined I/O pins, and you're facing a serious complexity issue.

In an effort to address signal-to-pin optimization, the DesignF/X tool enables fast, system-oriented optimization of signal-to-pin assignments in FPGAs and complex programmable-logic devices (CPLDs). Proper pin assignments minimize wire crossings and pc-board routing complexity, which in turn can reduce the number of required board layers and let the system run at higher clock rates.

The tool reduces the number of iterations needed to develop an optimized board. Using smart algorithms, it creates an accurate impact analysis and optimizes pin assignments before the design team creates symbols, schematics, and a pc-board layout. It also automatically handles differential pairs.

DesignF/X can be employed at the block-diagram stage to evaluate and optimize a design. Or, it can be used downstream at the onset of pc-board layout. Either way, it's a snap for FPGA or pc-board designers to specify mobility constraints, layer parking, and other properties.

Integrated with Cadence's Allegro PCB design platform, the tool supports Xilinx FPGAs. Available now, DesignF/X costs $15,000/year for a networked license.

Product Acceleration Inc.

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